An apparatus for nullifying the differential output offset voltage between the outputs of a differential amplifier and for setting the DC levels of the outputs to a known reference voltage includes a circuit which cross-couples the opposing AC output signals to obtain only the DC components of each signal. The apparatus further includes a first operational amplifier to generate a compensation voltage from the DC components of the outputs of the differential amplifier proportional to the amount of offset between the DC components of the outputs of the differential amplifier. The compensation voltage is fed back to the offset control inputs of the differential amplifier to reduce the differential offset voltage to substantially zero volts. The apparatus further includes a dual voltage divider network having a second operational amplifier that supplies a variable reference voltage to one terminal of each leg of the voltage divider network. The outputs of the differential amplifier each provided to a respective other terminal of the dual voltage divider network. The second operational amplifier has a reference voltage on one of its inputs. A signal responsive to the common mode output voltage from the differential amplifier is provided to the other input. The second operational amplifier provides an output voltage that is responsive to the common mode voltage output from the differential amplifier. The output voltage from the second operational amplifier provided to the terminals of the dual voltage divider network varies such that the voltage outputs from the voltage divider network have a common mode voltage substantially equal to the reference voltage.

Compensation circuit for nullifying differential offset voltage and regulating common mode voltage of differential signals

A burst mode digital data receiver automatically adjusts its logic reference voltage to be equal to one-half of the sum of the minimum and maximum excursions of a received data signal. The receiver includes a differential amplifier circuit which has a first input for receiving the data signal and a second input connected to a voltage reference circuit. The voltage reference circuit is responsive to an output signal from the amplifier circuit to produce the required logic reference voltage at the second input to the amplifier circuit by generating a feedback signal which causes the amplifier circuit to have a first gain value during the absence of the data signal and while the data signal is less than its peak amplitude and a second gain value approximately twice the first gain value for a predetermined time after the peak amplitude of the data signal is reached.

Burst mode digital data receiver

A dc-coupled packet mode digital data receiver for use with an optical bus, uses a peak detector(s) A2P, A2N to adaptively establish an instantaneous logic threshold at the beginning of a data burst. A reset circuit resets the peak detector(s) and other circuits of the receiver in response to an end-of-packet reset signal, thereby enabling the reception of closely-spaced burst data packets which have greatly differing power levels.

Packet mode digital data receiver

A receiver includes a first amplifying circuit for amplifying an input signal to thereby output an amplified input signal. A reference voltage generating circuit has the same configuration as the first amplifying circuit and generates a reference signal having a reference voltage for the amplified input signal. A variable-gain amplifying circuit variably adjusts the gain of the level of a signal derived from the amplified input signal and reference signal. The variable-gain amplifying circuit includes a second amplifying circuit for amplifying the amplified input signal and reference signal for maintaining linearity to thereby output a pair of first differential signals and a pair of second differential signals having shifted levels. A first differential amplifier performs differential amplification based on the first differential signals. A second differential amplifier performs differential amplification based on the first differential signals with a higher gain than the first differential amplifier. A gain controller controls, based on the second differential signals, the gains of the first and second differential amplifiers with a control signal capable of varying gain allocation to said the two differential amplifiers. When the amplified input signal has an amplitude far greater than the reference signal, the gain controller causes a current to flow through only one of the two differential amplifiers. When the amplified input signal has an amplitude far smaller than the reference signal, the gain controller causes the two differential amplifiers to operate at the same time.

Receiver capable of outputting a high quality signal without regard to an input signal level

A transresistance amplifier particularly adapted for use in a radiation detection system. The amplifier includes a feedback gain stage with a switched capacitor load. The amplifier is arranged to provide an average detector voltage approximating zero thus substantially reducing detector noise and also providing a low equivalent input impedance for increasing injection efficiency. A switched capacitor output load is also provided which allows the total transresistance to be determined by simply selecting an appropriate capacitance value.

Switched capacitor transresistance amplifier

A device for discriminating between two values of a signal using DC offset compensation including an automatic gain control circuit, a peak detector circuit and a feedback path from the peak detector circuit to the input circuit of the automatic gain control circuit. The value of the feedback current is regulated so that the maximum value of one of the same polarity signals and the opposite polarity signal coincides with the minimum value of the other of the two signals.

Device for discriminating between two values of a signal with DC offset compensation

PURPOSE:To pick up a timing signal from binary or ternary code, by obtaining an output signal of the 1st and 2nd level shift circuits which can change level shift amount and providing the 1st and 2nd differential amplifiers making slice of input waveform through the output signal of the level shift circuits. CONSTITUTION:Differential output signals (a), (b) of an equalizing amplifier circuit are as shown (A) for binary code and as shown (B) for ternary code. A binary/ternary control terminal 18 is grounded for binary code and opened for ternary code. Then, the level shift amount at level shift circuits 11, 12 can be changed. At a binary code, only a differential amplifier 13 is operated and no differential amplifier 14 is operative. Signals c-f respectively level-shfted at the circuits 11, 12 are given to the differential amplifiers 13, 14 and at binary code a signal (g) shown in (C) is outputted from an output terminal 19 and at ternary code, the signal (g) shown in (D) is outputted.

Timing pickup circuit

Vorrichtung zum unterscheiden zwischen zwei werten eines signals mit gleichstrom-versetzungskompensation

PURPOSE:To secure a decision for the binary code regardless of the occurrence probability of the mark factor of the binary code, by providing both an AGC circuit and a peak wave detecting circuit CONSTITUTION:The optical signals of ''0'' and ''1'' supplied from the light emitting diode 1 are received by the photodiode 2 and put into the current-voltage converting circuit 4 The output of the circuit 4 is put into the AGC circuit 5, and the signals of V- and V+ obtained through the output terminals 6 and 7 of the circuit 5 are supplied to the peak wave detecting circuit 8 The output of the circuit 8 feeds the peak wave detection output back to the circuit 4 via a resistance to set DELTAV (shift of center level of the same polarity V+ and opposite polarity V-) to zero

Direct current feedback system for binary code

PURPOSE:To control an unbalanced code, by the level shift of the same and opposite polarity signals made from an AGC amplifier receiving a PCM signal and making coincided the minimum value before the shift and the maximum value after the shift. CONSTITUTION:A PCM signal inputted to a terminal 1 is input to an AGC Amp 3. The same polarity signal outputted from the Amp 3 is outputted to a terminal 2 and also a terminal 17 of level shift circuits 4, 5, and the opposite polarity signal B is inputted to a terminal 18. A signal B is shifted for the level at a circuit 4 and a signal A is made so at a circuit 5, and the outputs are inputted to peak detection circuits 7, 8. The circuit 7 detects the peak of the difference between the minimum value of the signal A and the output of the circuit 4 and a DC control output in which the minimum value of the signal A and the output of the circuit 4 are detected for the defference of peak in a circuit 7 and charge is made with fast leading and discharge is made with a greater time constant, is fed back from a terminal 32 to the Amp 3. Similarly, a circuit 8 feeds back an AGC control output obtained from the minimum value of the signal B and the output of the circuit 5 from a terminal 40 to the Amp 3. With the constitution like this, an effective gain control can be made even with an unbalanced code.

Takahashi Motohide

Papers

Device for discriminating between two values of a signal with DC offset compensation

Timing pickup circuit

Vorrichtung zum unterscheiden zwischen zwei werten eines signals mit gleichstrom-versetzungskompensation

Direct current feedback system for binary code

Automatic gain control amplifier