We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.

Interpolation and SAT-based model checking

An integrated circuit device includes: a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block. The data line driver block includes first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups. The wordline control circuit drives an identical wordline N times from among the wordlines in one horizontal scan period of the display panel. The first to Nth divided data line drivers are disposed along a first direction in which the bitlines extend.

Integrated circuit device and electronic instrument

A threshold voltage distribution of a set of storage elements in a memory device is measured by sweeping a control gate voltage while measuring a characteristic of the set of storage elements as a whole (710). The characteristic indicates how many of the storage elements meet a given condition, such as being in a conductive state. For example, the characteristic may be a combined current, voltage or capacitance of the set which is measured at a common source of the set. The control gate voltage can be generated internally within a memory die. Similarly, the threshold voltage distribution can be determined internally within the memory die. Optionally, storage elements which become conductive can be locked out, such as by changing a bit line voltage, so they no longer contribute to the characteristic (715). New read reference voltages are determined based on the threshold voltage distribution to reduce errors in future read operations.

Measuring threshold voltage distribution in memory using an aggregate characteristic

A semiconductor integrated circuit includes a first wiring layer formed in a first direction, a second wiring layer formed in a second direction perpendicular to the first direction, and a third wiring layer formed in the second direction to sandwich the first wiring layer between the third wiring layer and the second wiring layer. The second and third wiring layers are shifted from each other by a predetermined distance in the first direction. An automatic layout method for a semiconductor integrated circuit, and a recording medium are also disclosed.

Semiconductor integrated circuit and semiconductor integrated circuit wiring layout method

An in-memory processor includes a memory array which stores data and an activation unit to activate at least two cells in a column of the memory array at generally the same time thereby to generate a Boolean function output of the data of the at least two cells. Another embodiment shows a content addressable memory (CAM) unit without any in-cell comparator circuitry.

Using storage cells to perform computation

PROBLEM TO BE SOLVED: To provide a semiconductor signal processor capable of carrying out quickly logic computation processing and arithmetic computation processing at a low electric power consumption in a narrow occupied area. SOLUTION: A unit operator cell is constituted of a plurality of SOI transistors, writing data are stored in body areas SNA, SNB of the at least two SOI transistors, and the storage SOI transistors NQ1, NQ2 are coupled in series or independently to a reading port RPRTB or RPRTA. An AND computation result or a NOT computation result of the storage data in the unit operator cell can be obtained by this manner, and the computation processing can be carried out only by writing and reading the data. COPYRIGHT: (C)2010,JPO&INPIT

Semiconductor signal processor

A BIST circuit conducts an operation test on a memory cell array to detect a defective memory cell when power is turned on. On the basis of a result of the operation test, the BIST circuit generates a redundancy code indicative of a defect address corresponding to a defective memory cell. The redundancy code is transmitted to a repair determining circuit in a decoding circuit. The repair determining circuit stores the redundancy code in a volatile manner during the power is on. When an input address coincides with the redundancy code to be stored on the inside, the repair determining circuit executes an access to a corresponding spare memory cell area.

Semiconductor memory device performing redundancy repair based on operation test and semiconductor integrated circuit device having the same

In a test interface circuit arranged between an embedded memory and a test data input/output (I/O) terminal, a first-in first-out circuit for successively storing test data is arranged for controlling a latency of data read from the embedded memory. The test interface circuit for the embedded memory can reduce the number of test data I/O terminals, and can increase the executable test patterns.

Test interface circuit and semiconductor integrated circuit device including the same

A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

Low-power consumption semiconductor memory device

A charge-transfer sense amplifier which is connected to a pair of bit lines includes a flip-flop type sense amplifier comprising cross-coupled transistors, a pair of charge transfer elements provided between the flip-flop type sense amplifier and the pair of bit lines, and elements for precharging nodes between the charge transfer elements and the flip-flop type sense amplifier to an "H" level. There is additionally provided a pair of coupling capacitances for capacitively coupling respective gates of the charge transfer elements to a pair of bit lines in a cross-coupling configuration. A circuit device for precharging respective gates of the charge transfer elements brings the charge transfer elements into substantially a cut-off state. This configuration enables the charge-transfer sense amplifier and a one-half Vcc precharge scheme to be effectively combined.

Kazutami Arimoto

Papers

Semiconductor signal processor

Semiconductor memory device performing redundancy repair based on operation test and semiconductor integrated circuit device having the same

Test interface circuit and semiconductor integrated circuit device including the same

Low-power consumption semiconductor memory device

Charge-transfer sense amplifier for dram and operating method therefor