Modern global routers employ various routing methods to improve routing speed and quality Maze routing is the most time-consuming process for existing global routing algorithms This paper presents two bounded-length maze routing (BLMR) algorithms (optimal-BLMR and heuristic-BLMR) that perform much faster routing than traditional maze routing algorithms In addition, a rectilinear Steiner minimum tree aware routing scheme is proposed to guide heuristic-BLMR and monotonic routing to build a routing tree with shorter wirelength This paper also proposes a parallel multithreaded collision-aware global router based on a previous sequential global router (SGR) Unlike the partitioning-based strategy, the proposed parallel router uses a task-based concurrency strategy Finally, a 3-D wirelength optimization technique is proposed to further refine the 3-D routing results Experimental results reveal that the proposed SGR uses less wirelength and runs faster than most of other state-of-the-art global routers with a different set of parameters , , ,  Compared to the proposed SGR, the proposed parallel router yields almost the same routing quality with average 271 and 312-fold speedup on overflow-free and hard-to-route cases, respectively, when running on a 4-core system

https://ir.nctu.edu.tw:443/bitstream/11536/21646/1/000318163800005.pdf

NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing

Given the significance of placement in IC physical design, extensive research studies performed over the last 50 years addressed numerous aspects of global and detailed placement. The objectives and the constraints dominant in placement have been revised many times over, and continue to evolve. Additionally, the increasing scale of placement instances affects the algorithms of choice for high-performance tools. We survey the history of placement research, the progress achieved up to now, and outstanding challenges.

Progress and challenges in VLSI placement research

Modern global routers use various routing methods to improve routing speed and the quality. Maze routing is the most time-consuming process for existing global routing algorithms. This paper presents two bounded-length maze routing (BLMR) algorithms (optimal-BLMR and heuristic-BLMR) to perform much faster routing than traditional maze routing algorithms. The proposed sequential global router, which adopts a heuristic-BLMR, identifies less-wirelength routing results with less runtime than state-of-the-art global routers. This study also proposes a parallel multi-threaded collision-aware global router based on a previous sequential global router. Unlike the conventional partition-based concurrency strategy, the proposed algorithm uses a task-based concurrency strategy. Experimental results reveal that the proposed sequential global router uses less wirelength and runs about 1.9X to 18.67X faster than other state-of-the-art global routers. Compared to the proposed sequential global router, the proposed parallel global router yields almost the same routing quality with average 2.71 and 3.12-fold speedup on overflow-free and hard-to-route benchmarks, respectively, when running on an Intel quad-core system.

Multi-threaded collision-aware global routing with bounded-length maze routing

Due to the significant mismatch between existing wirelength models and the congestion objective in placement, considering routability during placement is particularly significant for modern circuit designs. In this paper, a novel routability-driven analytical placement algorithm for large-scale mixed-size circuit designs is proposed. Unlike most existing works which usually optimize routability by reallocating whitespace or net-based congestion removal, the proposed algorithm optimizes routability from three major aspects: (1) Pin density: Most existing works optimize routability based on net distribution, while our work considers both the density of pins and their routing directions; (2) Routing overflow optimization: Unlike most previous works that use whitespace allocation or net-based congestion removal to improve routability, our work optimizes routing overflow by a novel sigmoid function during global placement; (3) Macro porosity consideration: A virtual macro expansion technique is applied to consider the constrained routing resource incurred by big macros. Routability-driven legalization and detailed placement are also proposed to further optimize routing congestion. Experimental results show the effectiveness and efficiency of our proposed algorithm. Compared with the participating teams for the 2011 ACM ISPD Routability-Driven Placement Contest, our algorithm achieves the best average overflow and routed wirelength.

Routability-driven analytical placement for mixed-size circuit designs

The Steiner minimal tree (SMT) problem is an NP-hard problem, which is the best connection model for a multi-terminal net in global routing problem. This paper presents a unified algorithm for octagonal and rectilinear SMT construction based on hybrid transformation strategy (HTS) and self-adapting particle swarm optimization. Firstly, an effective HTS is proposed to enlarge the search space and improve the convergence speed. Secondly, the proposed HTS in the evolutionary process may produce an ineffective solution, and consequently the crossover and mutation operators of genetic algorithm (GA) based on union-find sets is proposed. Thirdly, a self-adapting strategy that can adjust the acceleration coefficients is proposed to further improve the convergence and the quality of the proposed algorithm. Finally, the hybrid transformation can be applied to GA and the proposed algorithm can be applied to rectilinear architecture. To our best knowledge, the proposed algorithm is the first unified algorithm to solve the SMT construction under both octagonal and rectilinear architecture. The experimental results show that the proposed algorithm can efficiently provide a better solution for SMT problem both in octagonal and rectilinear architectures than others. Moreover, the algorithm can obtain several topologies of SMT, which is beneficial for optimizing congestion in VLSI global routing stage.

A unified algorithm based on HTS and self-adapting PSO for the construction of octagonal and rectilinear SMT

The increasing complexity of interconnection designs has enhanced the importance of research into global routing when seeking high-routability (low overflow) results or rapid search paths that report wirelength estimations to a placer. This work presents two routing techniques, namely circular fixed-ordering monotonic routing and evolution-based rip-up and rerouting using a two-stage cost function in a high-performance congestion-driven 2-D global router. We also propose two efficient via-minimization methods, namely congestion relaxation by layer shifting and rip-up and reassignment, for a dynamic programming-based layer assignment. Experimental results demonstrate that our router achieves performance similar to the first two winning routers in ISPD 2008 Routing Contest in terms of both routability and wirelength at a 1.05 × and 18.47 × faster routing speed. Moreover, the proposed layer assignment achieves fewer vias and shorter wirelength than congestion-constrained layer assignment (COLA).

https://ir.nctu.edu.tw:443/bitstream/11536/15610/1/000300511600007.pdf

NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing

The increasing complexity of interconnection designs has enhanced the importance of research into global routing when seeking high-routability (low overflow) results or rapid search paths that report wire-length estimations to a placer. This work presents two routing techniques, namely adaptive pseudorandom net-ordering routing and evolution-based rip-up and reroute using a two-stage cost function in a high-performance congestion-driven 2-D global router. We also propose two efficient via-minimization methods, namely congestion relaxation by layer shifting and rip-up and re-assignment, for a dynamic programming-based layer assignment. Experimental results demonstrate that our router achieves performance similar to the first two winning routers in ISPD 2008 Routing Contest in terms of both routability and wire length at a 1.42X and 25.84X faster routing speed. Besides, our layer assignment yields 3.5% to 5.6% fewer vias, 2.2% to 3.3% shorter wirelength and 13% to 27% less runtime than COLA.

/pdf/efficient-simulated-evolution-based-rerouting-and-congestion-80q7r9vouk.pdf

Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing

Placement profoundly impacts physical design owing to its role in determining the lower bound of a circuit wirelength, as well as the circuit routability To close the gap between placement and routing, this study integrates global routing and placement to improve the wirelength estimation accuracy of placement Two methods, called wirelength-reduced cell shifting and cell rearrangement by bipartite matching, are applied to minimize wirelength Cell sorting based congestion reduction and pattern-prerouting based congestion-avoided cell shifting are proposed to reduce congestion Experimental results demonstrate that the proposed placer improves total routed wirelength by 2% to ROOSTER on IBMv2 benchmarks Moreover, the proposed GRPlacer resolves the original congested regions of the placements generated by ROOSTER Compare with the detailed placer in ROOSTER, our work can reduce more routed wire length and remove more overflows

Ke-Ren Dai

Papers

NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing

Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing

GRPlacer: improving routability and wire-length of global routing with circuit replacement