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Journal ArticleDOI

NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing

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TLDR
This work presents two routing techniques, namely circular fixed-ordering monotonic routing and evolution-based rip-up and rerouting using a two-stage cost function in a high-performance congestion-driven 2-D global router and proposes two efficient via-minimization methods.
Abstract
The increasing complexity of interconnection designs has enhanced the importance of research into global routing when seeking high-routability (low overflow) results or rapid search paths that report wirelength estimations to a placer. This work presents two routing techniques, namely circular fixed-ordering monotonic routing and evolution-based rip-up and rerouting using a two-stage cost function in a high-performance congestion-driven 2-D global router. We also propose two efficient via-minimization methods, namely congestion relaxation by layer shifting and rip-up and reassignment, for a dynamic programming-based layer assignment. Experimental results demonstrate that our router achieves performance similar to the first two winning routers in ISPD 2008 Routing Contest in terms of both routability and wirelength at a 1.05 × and 18.47 × faster routing speed. Moreover, the proposed layer assignment achieves fewer vias and shorter wirelength than congestion-constrained layer assignment (COLA).

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Citations
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Journal ArticleDOI

NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing

TL;DR: Two bounded-length maze routing (BLMR) algorithms are presented that perform much faster routing than traditional maze routing algorithms and a rectilinear Steiner minimum tree aware routing scheme is proposed to guide heuristic-BLMR and monotonic routing to build a routing tree with shorter wirelength.
Journal ArticleDOI

A unified algorithm based on HTS and self-adapting PSO for the construction of octagonal and rectilinear SMT

TL;DR: The proposed algorithm is the first unified algorithm to solve the SMT construction under both octagonal and rectilinear architecture and can obtain several topologies of SMT, which is beneficial for optimizing congestion in VLSI global routing stage.
Proceedings ArticleDOI

A parallel integer programming approach to global routing

TL;DR: A flexible and highly scalable distributed algorithm for global routing that concurrently processes routing subproblems corresponding to rectangular subregions covering the chip area that generates higher quality solutions than competing methods in the open literature.
Journal ArticleDOI

NTHU-Route 2.0: A Robust Global Router for Modern Designs

TL;DR: A robust global router called NTHU-Route 2.0 is presented that improves the solution quality and runtime of NTHu-Route by the following enhancements: 1) a new history based cost function; 2) new ordering methods for congested region identification and rip-up and reroute; and 3) two implementation techniques.
Journal ArticleDOI

XGRouter: high-quality global router in X-architecture with particle swarm optimization

TL;DR: To the best knowledge, XGRouter is the first work to use a concurrent algorithm to solve the global routing problem in X-architecture and can produce solutions of higher quality than other global routers.
References
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Book

Introduction to Algorithms

TL;DR: The updated new edition of the classic Introduction to Algorithms is intended primarily for use in undergraduate or graduate courses in algorithms or data structures and presents a rich variety of algorithms and covers them in considerable depth while making their design and analysis accessible to all levels of readers.
Journal ArticleDOI

An Algorithm for Path Connections and Its Applications

TL;DR: The algorithm described in this paper is the outcome of an endeavor to answer the following question: Is it possible to find procedures which would enable a computer to solve efficiently path-connection problems inherent in logical drawing, wiring diagramming, and optimal route finding?
Proceedings ArticleDOI

PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs

TL;DR: PathFinder as mentioned in this paper uses an iterative algorithm that converges to a solution in which all signals are routed while achieving close to the optimal performance allowed by the placement, which is achieved by forcing signals to negotiate for a resource and thereby determine which signal needs the resource most.
Journal ArticleDOI

FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design

TL;DR: It is shown experimentally that, over 18 industrial circuits in the ISPD98 benchmark suite, FLUTE with default accuracy is more accurate than the Batched 1-Steiner heuristic and is almost as fast as a very efficient implementation of Prim's rectilinear minimum spanning tree algorithm.
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