The invention relates to a chip parameter multi-programming circuit based on a fuse technology The circuit includes a burn commander; four fuses; four MOS transistors, the gate of each MOS transistoris connected with a burn-off instructor and receives a burn-off instruction; A first fuse is connected between the drain of the first MOS transistor and the drain of the second MOS transistor, a second fuse is connected between the source of the first MOS transistor and the source of the second MOS transistor, the drain of the first MOS transistor is connected with the first resistance, the drainof the second MOS transistor is connected with the second resistance, the source of the first MOS transistor is connected with the third resistance, and the source of the second MOS transistor is connected with the fourth resistance and connected with the positive electrode of the comparator; A third fuse is connected between the drain of the third MOS transistor and the drain of the fourth MOS transistor, A fourth fuse is connected between the source of the third MOS transistor and the source of the fourth MOS transistor, the drain of the third MOS transistor is connected with a fifth resistor, the drain of the fourth MOS transistor is connected with a sixth resistor, the source of the third MOS transistor is connected with a seventh resistor, and the source of the second MOS transistoris connected with an eighth resistor and connected with a negative electrode of the comparator

A chip parameter multi-programming circuit based on a fuse technology

A memory device may include the following elements: a first memory cell; a first word line for transmitting a first control signal to control an electrical connection in the first memory cell; a first bit line connected to the first memory cell; a first transistor, wherein a first terminal of the first transistor is connected to the first bit line; a second memory cell; a second word line for transmitting a second control signal to control an electrical connection in the second memory cell; a second bit line connected to the second memory cell; a second transistor, wherein a first terminal of the second transistor is connected to the second bit line; and a sense amplifier having a first input terminal connected to a second terminal of the first transistor and having a second input terminal connected to a second terminal of the second transistor.

Memory device, related method, and related electronic device

The present invention provides a memory unit and a method for controlling the memory unit The memory cell includes a first charge storage transistor and a second charge storage transistor The firstcharge storage transistor includes a substrate, a first end is coupled to a first bit line, a second end is coupled to a signal line, a control end is coupled to a word line, and a dielectric layer isformed between the substrate of the first charge storage transistor and the control terminal of the first charge storage transistor The second charge storage transistor includes a substrate, a firstend is coupled to the signal line, a second end is coupled to the second bit line, and a control end is coupled to the word line The dielectric layer is formed between the substrate of the second charge storage transistor and the control end of the second charge storage transistor The invention can effectively reduce the size of integrated circuits in applications, and can be applied to integrated circuit chips that require lower power consumption

Memory unit and method for controlling memory unit

A memory system includes a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array, a bl transistor electrically coupled to the first bitline, wherein the bl transistor is configured to receive as input a first electrical signal from the first bitline, and a blb transistor electrically coupled to the second bitline, wherein the blb transistor is configured to receive as input a second electrical signal from the second bitline, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor.

Bitline-driven sense amplifier clocking scheme

An array of memory cells in rows and columns with each column having a corresponding reference cell and a corresponding comparator. Each memory cell in a given row and given column is connected to a memory wordline for the row and to a memory bitline for the column. Each reference cell is connected to a reference wordline for the reference cells and to a reference bitline. Each comparator for a column has a current mirror with a reference section connected to the reference bitline for the reference cell for the column and a memory section connected to the memory bitline for the memory cells in the column. Each reference section has a current mirror node and all current mirror nodes in the array are connected to reduce mismatch and improve sensing accuracy. Voltages applied to the memory and reference wordlines are varied to provide accurate single-ended sensing, margin testing, etc.

Memory array including distributed reference cells for current sensing

A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.

Dual-bit 3-t high density mtprom array

A multi-time programmable memory (MTPM) memory cell and method of operating Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT

Kempanna Thejas

Papers

Dual-bit 3-t high density mtprom array

Dual-bit 3-t high density mtprom array and method of operation thereof