A secure demand paging system ( 1020 ) includes a processor ( 1030 ) operable for executing instructions, an internal memory ( 1034 ) for a first page in a first virtual machine context, an external memory ( 1024 ) for a second page in a second virtual machine context, and a security circuit ( 1038 ) coupled to the processor ( 1030 ) and to the internal memory ( 1034 ) for maintaining the first page secure in the internal memory ( 1034 ). The processor ( 1030 ) is operable to execute sets of instructions representing: a central controller ( 4210 ), an abort handler ( 4260 ) coupled to supply to the central controller ( 4210 ) at least one signal representing a page fault by an instruction in the processor ( 1030 ), a scavenger ( 4220 ) responsive to the central controller ( 4210 ) and operable to identify the first page as a page to free, a virtual machine context switcher ( 4230 ) responsive to the central controller ( 4210 ) to change from the first virtual machine context to the second virtual machine context; and a swapper manager ( 4240 ) operable to swap in the second page from the external memory ( 1024 ) with decryption and integrity check, to the internal memory ( 1034 ) in place of the first page.

Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices

The disclosed invention is a method and apparatus for use in handling interrupts in a data processing system where the kernel is preemptible, has real-time scheduling ability, and which supports multithreading and tightly-coupled multiprocessors. The invention more specifically provides a technique for servicing interrupts in a processor by means of kernel interrupt handler threads which service the interrupt from start to finish. For efficiency, the interrupt handler threads do not require a complete context switch unless the interrupt handler thread is blocked. The kernel makes use of preprepared interrupt handler threads for additional efficiency, and these interrupt handler threads are not subjected to inordinate delays caused by the phenomenon of interrupt priority inversion if they do become blocked.

Apparatus and method for interrupt handling in a multi-threaded operating system kernel

A memory management and protection system for realizing a high speed execution and a proper and flexible memory access control for multiple programs sharing an identical logical address space. In the system, the memory access is permitted according to a segment identifier identifying a segment in the logical address space, and a memory protection information for a region in each segment including a target right permission to indicate assigned rights to make a memory access from the region to each of the segments, and an execution permission to indicate a type of the memory access permitted by the right permission. Alternatively, a memory access can be permitted by using an access control list to be attached to each address table entry, which stores a plurality of program numbers identifying programs which are permitted to make accesses to the logical address stored in each address table entry, among which one that matches with the current program number is to be searched. Also, it is preferable to allocate a plurality of programs within a limit of available memory protection capacity to an identical logical address space, without any overlap between adjacently allocated address regions.

Memory management and protection system for virtual memory in computer system

A distributed computer system, has a number of users and target applications. When a user logs on to the system, an authentication unit issues the user with a privilege attribute certificate (PAC) representing the user's access rights. When the user wishes to access a target application, he presents the PAC to that application as evidence of his access rights. The application, in turn, passes the PAC to a PAC use monitor (PUM) which validates the PAC. The PUM is shared between a plurality of applications.

Access control in a distributed computer system

A system and method for detecting and recording events related to the quality of service experienced by a wireless device in a wireless network. In one example, these events may be detected and recorded by the wireless device, without support from the network. Performance monitoring tests may be initiated by the wireless device at the direction of a management server, independent of the network in which the device may be operating. The wireless device may store the results of these tests and report the results to the management server.

System and method for service quality management for wireless devices

Two or more address spaces are provided in a data processor. One of the address spaces comprises control registers so that the control registers can be accessed using instructions having an address in the second address space. High-speed context switching can be accomplished by allotting the context-saving area to the second address space. The context can be saved in various formats specified by a context format register.

Multiple address-space data processor with addressable register and context switching

A data processor that executes arithmetic operations between first and second binary numbers, stored in different registers, of different lengths, with the first number having a byte-length smaller than the register, and the second number having a byte-length equal to the register, by storing the first number so that its lower order bit is justified with the lower order bit of the second number. Additionally, data having different bit and byte polarities are processed by reversing the bit and byte order of the data as required.

System for processing data having different formats

A data processor executes the exception process, interrupt process and the trap instruction of internal interrupt instructions in a unified manner. The data processor is adapted to read an internal state variable simultaneously with reading the head address of an EIT process handler from an external memory when an EIT process is started so that it enables the internal state to be set on the basis of the information of the variable when the EIT process handler starts. The data processor is provided with multiple EIT process means which, when a plurality of EIT process requests are generated, decides the process order on the basis of priority from the content of the request. The data processor is also provided with means which specially treats the EIT process acceptance condition after returning from one EIT process handler, and thereby is generously free in programming.

Exception, interrupt, and trap handling apparatus which fetches addressing and context data using a single instruction following an interrupt

A data processor which has an operand instruction having an operation code specifying portion to specify the kind of operation and an effective address specifying field showing the effective address of the operand, so that an additional mode specifying field to perform the extension modification of addressing can be added to an addressing mode shown by the effective address specifying field, whereby even when the address modification extension is carried out at multiple levels, the address calculation can sequentially be performed while reading each part of the operand, thereby improving the execution speed of program and facilitating complier structure.

Instruction format with sequentially performable operand address extension modification

The invention provides a novel data processor containing specific instructions including that which invalidates the content or branch records stored in cache memory, instruction queue, instruction pipeline, and branch prediction mechanism, and that which fetches and executed instructions having propriety, so that the data processor to securely coordinate the instruction string of main memory and those instructions to be actually processed, thus eventually preventing the instruction pipelines from conflict between them.

Ken Sakamura

Papers

Multiple address-space data processor with addressable register and context switching

System for processing data having different formats

Exception, interrupt, and trap handling apparatus which fetches addressing and context data using a single instruction following an interrupt

Instruction format with sequentially performable operand address extension modification

Data processor for invalidating prefetched instruction or branch history information