Patent
Multiple address-space data processor with addressable register and context switching
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TLDR
In this paper, the authors propose to allocate the context-saving area to the second address space for high-speed context switching, which can be accomplished by using context format registers.Abstract:
Two or more address spaces are provided in a data processor. One of the address spaces comprises control registers so that the control registers can be accessed using instructions having an address in the second address space. High-speed context switching can be accomplished by allotting the context-saving area to the second address space. The context can be saved in various formats specified by a context format register.read more
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Apparatuses and methods for performing logical operations using sensing circuitry
TL;DR: In this paper, the authors present an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array, which can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, and perform a number of intermediate operation phases of the logical operation.
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Apparatuses and methods for performing compare operations using sensing circuitry
TL;DR: In this paper, the authors present apparatuses and methods related to performing compare and/or report operations using sensing circuitry, such as charging an input/output (IO) line of a memory array to a voltage.
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Division operations for memory
TL;DR: In this article, the present disclosure provides apparatuses and methods for performing division operations in a memory, including a first address space comprising a first number of memory cells coupled to a sense line and to a second number of select lines wherein the second address space stores a divisor value.
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Secure computer system having privileged and unprivileged memories
TL;DR: Gating circuitry as mentioned in this paper prevents the exposure of instructions and data form the privileged memory from appearing outside of the secure module, and the gating circuits switch address spaces by recognizing a sequence of predetermined addresses.
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Independently addressable memory array address spaces
TL;DR: In this article, the authors present devices and methods for accessing a memory array address space, including a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines, and a second address space consisting memory cells coupling to a second number of selected lines and the number of senses.
References
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Patent
Memory back-up system
TL;DR: In this article, a non-write-through cache memory associated with each of the system's processing elements stores computations generated by that processing element, and at a context switch, the stored information is sequentially written to two separate main memory units.
Patent
A method and apparatus for coordinating execution of an instruction by a coprocessor
John Zolnowsky,Gruess Michael,David S. Mothersole,Stanley E. Groves,Douglas B. MacGregor,Van B. Shahan,Donald L. Tietjen +6 more
TL;DR: In this article, a system for interfacing a Processor to a Coprocessor using standard bus cycles is presented, where the Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coproprocessor designated by a CopROcessor Identity field in the operation word.
Patent
Direct-execution microprogrammable microprocessor system
Andrew J. McCrocklin,Nicholas E. Aneshansley,Patricia Shanahan,James J. Whelan,Jeffrey Paul Anderson,James E. Kocol,Gary L. Riddle +6 more
TL;DR: In this paper, a direct execution microprogrammable microprocessor system uses an emulatory micro programmable micro processor for direct execution of microinstructions in main memory through a microinstruction port.
Patent
Apparatus for addressing a larger number of instruction addressable central processor registers than can be identified by a program instruction
TL;DR: In this article, each pointer is associated with and corresponds to one of a limited number of general purpose registers addressable by various fields in a program instruction of the data processing system, and the data in the hardware register is made immediately available to the CPU before completion of the access to main storage.
Patent
Automatic context switching in a multiprogrammed multiprocessor system
TL;DR: In this paper, an interface between a central processing unit and a peripheral processing unit responds to a program instruction of either system call and proceed and wait, and interlocking is provided for directing to a reserved address in memory.