A high power MOSFET is disclosed in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip which are controlled by the same gate. The channels lead from the source electrodes to a relatively low resistivity region and from there to a relatively high resistivity epitaxially formed region which is deposited on a high conductivity substrate. The drain electrode may be either on the opposite surface of the chip or laterally displaced from and on the same side as the source regions. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain has a relatively high conductivity, thereby to substantially reduce the on-resistance of the device without effecting the breakdown voltage of the device. The breakdown voltage of the device is substantially increased by forming a relatively deep p-type diffusion with a large radius in the n-type epitaxial layer beneath each of the sources.

High power MOSFET with low on-resistance and high breakdown voltage

An insulated gate field effect transistor formed in one surface of a semiconductor substrate (1) has a channel, the surface portion of which has an impurity (9) with a conductivity type opposite to that of the substrate (1), and the deeper portion of which has an impurity (8) of the same conductivity type to the substrate. Moreover, the source and/or the drain (6, 7) of the transistor has an impurity layer of a conductivity type opposite to that of the substrate, with an impurity distribution (13, 14) gently sloped. The use of such impurity distributions overcomes the problems of the short-channel effect and reduction of the source-drain breakdown voltage which are present in standard devices. This enables a shorter channel to be used for a given source-drain breakdown voltage which is of advantage in a LSI having a high density of integration.

Insulated gate field effect transistor

High voltage, high frequency metal oxide semiconductor device having a precisely controlled channel extending to the surface and in which a metallization overlies a thick insulating layer and substantially covers the depletion region in the drain for breakdown voltage control.

High voltage, high frequency double diffused metal oxide semiconductor device

Enhancement-mode field-effect transistors (FETs) and depletion-mode FETs are provided on the same semiconductive substrate using five basic, lithographic, pattern-delineating steps. The five lithographic masking steps delineate in order: (1) the field isolation regions; (2) the enhancement-mode FET gate electrodes; (3) the depletion-mode FET gate electrodes; (4) contact holes or vias to FET source and drain regions and to depletion-mode FET gates; and (5) the high electrical conductivity metallic-type interconnection pattern. The low-concentration doping required to form the depletion-mode channel regions is provided after the second but before the third pattern delineation step, while the high-concentration doping to form the source and drain regions is provided after the third pattern delineation step. In order to obtain the desired device structure, it is necessary to use two separately defined polycrystalline silicon regions for the gate electrodes of the enhancement-mode and depletion-mode FETs. Using the five basic lithographic masking steps, FET integrated circuits can be fabricated that contain both enhancement-mode and depletion-mode FETs interconnected as desired.

Fabrication of integrated circuits containing enhancement-mode FETs and depletion-mode FETs with two layers of polycrystalline silicon utilizing five basic pattern delineating steps

A VDMOS structure with an added n- doping component, and a LOCOS oxide self-aligned to it, at the surface extension of the drain. The additional shallow n- component permits the body diffusion to be heavier, and hence reduces the risk of latchup.

Structure and process for reducing the on-resistance of mos-gated power devices

An MIS FET device and method of making the same wherein a device of nominal topology is made capable of sustaining drain to source potentials substantially higher than the normal breakdown potentials of prior art devices. The present invention is constructed with linearly graded PN junctions and the diffusion profile, as related to the geometry of the gate, is such that the junction depletion layer will extend into the drain region to a point under the thick field oxide so that a critical electric field is not produced in the thin gate oxide causing rupture thereof.

High-voltage mos transistor method and apparatus

A novel MISFET and method of manufacture involving a five mask process suitable for making N-channel devices alone, P-channel devices alone or both N and P-channel devices simultaneously. Novel topside contact means, field inversion protection means and gate breakdown protection means are disclosed.

Kenneth J. Moyle

Papers

High-voltage mos transistor method and apparatus

MISFET and method of manufacture