Patent
High-voltage mos transistor method and apparatus
Kenneth J. Moyle,Lee P Madden +1 more
TLDR
In this article, a MIS FET is constructed with linearly graded PN junctions and the diffusion profile, as related to the geometry of the gate, is such that the junction depletion layer will extend into the drain region to a point under the thick field oxide so that a critical electric field is not produced in the thin gate oxide causing rupture thereof.Abstract:
An MIS FET device and method of making the same wherein a device of nominal topology is made capable of sustaining drain to source potentials substantially higher than the normal breakdown potentials of prior art devices. The present invention is constructed with linearly graded PN junctions and the diffusion profile, as related to the geometry of the gate, is such that the junction depletion layer will extend into the drain region to a point under the thick field oxide so that a critical electric field is not produced in the thin gate oxide causing rupture thereof.read more
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Patent
High power MOSFET with low on-resistance and high breakdown voltage
Alexander Lidow,Thomas Herman +1 more
TL;DR: In this paper, a high power MOSFET is disclosed in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip which are controlled by the same gate.
Patent
Insulated gate field effect transistor
TL;DR: In this article, an insulated gate field effect transistor formed in one surface of a semiconductor substrate (1) has a channel, the surface portion of which has an impurity (9) with a conductivity type opposite to that of the substrate, and the deeper portion of the same conductivity types to the substrate.
Patent
High voltage, high frequency double diffused metal oxide semiconductor device
TL;DR: In this article, a high voltage, high frequency metal oxide semiconductor device having a precisely controlled channel extending to the surface and in which a metallization overlies a thick insulating layer and substantially covers the depletion region in the drain for breakdown voltage control is described.
Patent
Structure and process for reducing the on-resistance of mos-gated power devices
TL;DR: In this paper, a VDMOS structure with an added n- doping component, and a LOCOS oxide self-aligned to it, at the surface extension of the drain, is presented.
Patent
Structure for high breakdown PN diode with relatively high surface doping
TL;DR: In this article, a high voltage PN junction in which a surface layer of the more lightly doped side of the junction, adjacent to the heavily doped part of junction, is doped more heavily than the rest of that region and with the same conductivity type, is formed so that an overlying field plate totally depletes it before critical field for avalanche is reached.