Showing papers by "Kenneth Steiglitz published in 1994"
12 Jun 1994
TL;DR: A model and an optimization algorithm based on dynamic programming for choosing the mobility tracking scheme on a per-user basis are provided and are shown to be applicable to a very general class of problems.
Abstract: In personal communications applications, users communicate via wireless with a wireline network. The wireline network tracks the current location of the user, and can therefore route messages to a user regardless of the user's location. In addition to its impact on signaling within the wireline network, mobility tracking requires the expenditure of wireless resources as well, including the power consumption of the portable units carried by the users and the radio bandwidth used for registration and paging. Ideally, the mobility tracking scheme used for each user should depend on the user's call and mobility pattern, so that the current registration area approach (which ignores such information) may be wasteful of wireless resources under certain circumstances. In the paper, the authors provide a model and an optimization algorithm based on dynamic programming for choosing the mobility tracking scheme on a per-user basis. While illustrative results are provided for a simple one-dimensional mobility model, the approach is shown to be applicable to a very general class of problems. >
33 citations
Journal Article•
TL;DR: This paper describes several practical calculations which can be carried out in a highly parallel way in a single cellular automaton, including addition, subtraction, multiplication, arbitrarily nested combinations of these operations, and nite-impulse-response digital ltering of a signal arriving in a continuous stream.
Abstract: In this paper we show how to embed practical computation in onedimensional cellular automata using a model of computation based on collisions of moving particles. The cellular automata have small neighborhoods, and state spaces which are binary occupancy vectors. They can be fabricated in VLSI, and perhaps also in bulk media which support appropriate particle propagation and collisions. The model uses injected particles to represent both data and processors. Consequently, realizations are highly programmable, and do not have applicationspeci c topology, in contrast with systolic arrays. We describe several practical calculations which can be carried out in a highly parallel way in a single cellular automaton, including addition, subtraction, multiplication, arbitrarily nested combinations of these operations, and nite-impulse-response digital ltering of a signal arriving in a continuous stream. These are all accomplished in time linear in the number of input bits, and with xed-point arithmetic of arbitrary precision, independent of the hardware. Richard Squier is with the Computer Science Department at Georgetown University, Washington DC 20057. Ken Steiglitz is with the Computer Science Department at Princeton University, Princeton NJ 08544.
32 citations
31 Jan 1994
TL;DR: FAST overcomes some of the difficulties imposed by the very high complexity of interesting scientific algorithms, collects profile information representative of the algorithms rather than the underlying mapping strategies and hardware design choices, and allows a performance assessment of parallel machines with various sites and different interconnection schemes.
Abstract: We extend the practical range of simulations of parallel executions by "functional algorithm simulation," that is, simulation without actually performing most of the numerical computations involved. We achieve this by introducing a new approach for generating and collecting communication and computation characteristics for a class of parallel scientific algorithms. We describe FAST (Fast Algorithm Simulation Testbed), a prototype system that we developed to implement and test our approach. FAST overcomes some of the difficulties imposed by the very high complexity of interesting scientific algorithms, collects profile information representative of the algorithms rather than the underlying mapping strategies and hardware design choices, and allows a performance assessment of parallel machines with various sites and different interconnection schemes. >
15 citations
26 Oct 1994
TL;DR: Modifications are presented to existing clustering and mapping algorithms which improve their efficiency and running-time for the practical models adopted and new heuristics are necessary that will take into account more practical models of communication costs.
Abstract: This paper presents a comparison study of popular clustering and mapping heuristics which are used to map task-flow graphs to message-passing multiprocessors. To this end, we use task-graphs which are representative of important scientific algorithms running on data-sets of practical interest. The annotation which assigns weights to nodes and edges of the task-graphs is realistic. It reflects current trends in processor, communication channel, and message-passing interface technology and takes into consideration hardware characteristics of state-of-the-art multiprocessors. Our experiments show that applying realistic models for task-graph annotation affects the effectiveness and functionality of clustering and mapping techniques. Therefore, new heuristics are necessary that will take into account more practical models of communication costs. We present modifications to existing clustering and mapping algorithms which improve their efficiency and running-time for the practical models adopted. >
13 citations
TL;DR: You have obtained prior permission, you may not download an entire issue of a journal or multiple copies of articles, and you may use content in the JSTOR archive only for your personal, non-commercial use.
Abstract: you have obtained prior permission, you may not download an entire issue of a journal or multiple copies of articles, and you may use content in the JSTOR archive only for your personal, non-commercial use. Each copy of any part of a JSTOR transmission must contain the same copyright notice that appears on the screen or printed page of such transmission. JSTOR is a not-for-profit organization founded in 1995 to build trusted digital archives for scholarship. We work with the scholarly community to preserve their work and the materials they rely upon, and to build a common research platform that promotes the discovery and use of these resources. For more information about JSTOR, please contact support@jstor.org.
9 citations
02 May 1994
TL;DR: The paper compares two parallel architectures in terms of throughput versus cost, showing that there is a cost below which one architecture is an order of magnitude faster than the other, and above which this relationship is reversed.
Abstract: The paper compares two parallel architectures in terms of throughput versus cost. Throughput is estimated using machine parameters extracted from detailed models of each architecture. Cost models are used to express total resource use in terms of a common unit. Performance of an architecture is then evaluated by optimizing throughput for each possible cost. Finally, these throughput-versus-cost results for the two architectures are compared for a particular class of problems: iterative computations on a 2-dimensional grid. The results show that there is a cost below which one architecture is an order of magnitude faster than the other, and above which this relationship is reversed. This approach may prove useful as a general comparison methodology. >
TL;DR: The resulting performance curves for the two architectures show that there is a cost below which the pipelined architecture is an order of magnitude faster than the mesh, and above which this relationship is reversed.