MPEG-4 is the multimedia standard for combining interactivity, natural and synthetic digital video, audio and computer-graphics Typical applications are: internet, video conferencing, mobile videophones, multimedia cooperative work, teleteaching and games With MPEG-4 the next step from block-based video (ISO/IEC MPEG-1, MPEG-2, CCITT H261, ITU-T H263) to arbitrarily-shaped visual objects is taken This significant step demands a new methodology for system analysis and design to meet the considerably higher flexibility of MPEG-4 Motion estimation is a central part of MPEG-1/2/4 and H261/H263 video compression standards and has attracted much attention in research and industry, for the following reasons: it is computationally the most demanding algorithm of a video encoder (about 60-80% of the total computation time), it has a high impact on the visual quality of a video encoder, and it is not standardized, thus being open to competition Algorithms, Complexity Analysis, and VLSI Architectures for MPEG-4 Motion Estimation covers in detail every single step in the design of a MPEG-1/2/4 or H261/H263 compliant video encoder: Fast motion estimation algorithms Complexity analysis tools Detailed complexity analysis of a software implementation of MPEG-4 video Complexity and visual quality analysis of fast motion estimation algorithms within MPEG-4 Design space on motion estimation VLSI architectures Detailed VLSI design examples of (1) a high throughput and (2) a low-power MPEG-4 motion estimator Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation is an important introduction to numerous algorithmic, architectural and system design aspects of the multimedia standard MPEG-4 As such, all researchers, students and practitioners working in image processing, video coding or system and VLSI design will find this book of interest

Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation

This work explores the data reuse properties of full-search block-matching (FSBM) for motion estimation (ME) and associated architecture designs, as well as memory bandwidth requirements. Memory bandwidth in high-quality video is a major bottleneck to designing an implementable architecture because of large frame size and search range. First, the memory bandwidth in ME is analyzed and the problem is solved by exploring data reuse. Four levels are defined according to the degree of data reuse for previous frame access. With the highest level of data reuse, one-access for frame pixels is achieved. A scheduling strategy is also applied to data reuse of the ME architecture designs and a seven-type classification system is developed that can accommodate most published ME architectures. This classification can simplify the work of designers in designing more cost-effective ME architectures, while simultaneously minimizing memory bandwidth. Finally, a FSBM architecture suitable for high quality HDTV video with a minimum memory bandwidth feature is proposed. Our architecture is able to achieve 100% hardware efficiency while preserving minimum I/O pin count, low local memory size, and bandwidth.

https://ir.nctu.edu.tw:443/bitstream/11536/29135/1/000173716500006.pdf

On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture

A parallel vector-quantization (VQ) processor has been developed aiming at real-time compression of motion pictures using a 0.35-/spl mu/m triple-metal CMOS technology. The chip employs a new search algorithm for VQ encoding to reduce hardware volume. As a result, the die area of the chip is decreased to only 33% of that of conventional fully parallel design. This chip can handle 2048 template vectors by a single chip and is applicable to real-time compression of 30 frames/s full-color VGA (640/spl times/480 pixels) images. The chip operates at 33 MHz with power dissipation of 790 mW under 2.5-V power supply. A real-time motion picture compression system is demonstrated as an application of the chip. This system can transmit five full-color QVGA (320/spl times/240 pixels) images per second below 64 kb/s.

A parallel vector quantization processor eliminating redundant calculations for real-time motion picture compression

Eliminating Redundant Calculations for Real-time Motion Picture Compression

This paper presents two efficient very large scale integration (VLSI) architectures and buffer size optimization for full-search block matching algorithms. Starting from an overlapped data flow of search area, both systolic- and semisystolic-array architectural solutions are derived. By means of exploiting stream memory banks, not only input/output (I/O) bandwidth can be minimized, but also processor element efficiency can be improved. In addition, the controller structure for both solutions are very straightforward, making them very suitable for VLSI implementation to meet computational requirements. Moreover, by exploring the dependency graph, we focus on the problem of reducing the internal buffer size under minimal I/O bandwidth constraint to derive guidelines on reducing redundant internal buffer as well as to achieve area-efficient VLSI architectures. Simulation results show that, for N=P=16 (N is the reference block size and P is the search range), I/O bandwidth can be reduced by 2.4 times, while buffer size increases less than 38%. Two prototype chips for N=P=16 have been designed and fabricated. Test results show that clock rate can be up to 90 MHz, implying that more than 87.9-K motion vectors per second can be achieved to meet real-time requirements specified in MPEG-2 MP@ML coding standard.

https://ir.nctu.edu.tw:443/bitstream/11536/31095/1/000082280400007.pdf

Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms

This paper presents a new systolic architecture that can be used to realize the full-search vector quantization (VQ) encoder for high-speed applications. The architecture possesses the features of regularity and modularity, and is thus very suitable for VLSI implementation. For a codebook of size N and dimension k, the VQ encoder has an area complexity of O(N), a time complexity of O(k), and I/O bandwidth of O(k). It reaches a compromise between the hardware cost and speed performance as compared to existing systolic/regular VQ encoders. At the current state of VLSI technology, the proposed system can easily be realized in a single chip for most practical applications. In addition, it provides flexibility in changing the codebook contents and extending the codebook size, where the latter is achieved simply by cascading some identical basic chips. With 0.8 /spl mu/m CMOS technology to implement the proposed VQ encoder for the case of N=256, K=16, and an input data wordlength of 8 bit, the chip requires a die size of about 5.5/spl times/8.9 mm/sup 2/ and is able for processing 6.25 M data vectors (or 100 M data samples) every second. These features show that the proposed architecture is attractive for use in high-speed image/video applications.

A new VLSI architecture for full-search vector quantization

This paper presents a new systolic VLSI architecture to realize the full-search block matching algorithm for motion estimation. The architecture has an efficiency of 100 percent and a throughput of one motion vector per n/sup 2/ cycles, where n/spl times/n is the reference block size. As compared to existing VLSI motion estimators with the same efficiency and throughput, the proposed one not only gains advantages in the flexibility of changing the reference block size and the tracking range, but also employs no additional control circuitry to determine the motion vectors. These features make it useful for a wide range of applications.

A high-throughput, flexible VLSI architecture for motion estimation

This paper presents a new systolic architecture to realize the encoder of the full-search vector quantization (VQ) for high-speed applications. The architecture possesses the features of regularity and modularity, and is thus very suitable for VLSI implementation. For a codebook of size N and dimension k, the VQ encoder has area complexity of O(N), time complexity of O(k), and I/O bandwidth of O(k). It reaches a compromise between hardware cost and speed requirement as compared to existing systolic/regular VQ encoders. At the current state of VLSI technology, the proposed system can easily be realized in a single chip for most practical applications. In addition, it provides flexibility in changing the codebook contents and extending the codebook size, where the latter is achieved simply by cascading some identical basic chips. With 0.8 micrometers CMOS technology to implement the proposed VQ encoder for N equals 256 and k equals 16, the die size required is about 5 X 8.5 mm2 and the processing speed is up to 100 M samples per second. These features show that the proposed architecture is attractive for use in high-speed image/video applications.© (1995) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Ker-Min Chen

Papers

A new VLSI architecture for full-search vector quantization

A high-throughput, flexible VLSI architecture for motion estimation

New VLSI architecture for full-search vector quantization