Showing papers by "Kewal K. Saluja published in 1994"

Power constraint scheduling of tests

Abstract: This paper presents motivation for considering the power constraint in testing and gives a model-based formulation of the new test scheduling problem. Optimum test scheduling algorithms are presented for both equal and unequal test length cases under the power constraint. The algorithms consist of three basic steps. First, we find a complete set of time compatible tests with power dissipation information associated with each test. Second, from these tests, we extract the lists of power compatible tests. And finally, we use a minimum cover table approach to find the optimal scheduling of the tests. >

Sequential test generation with reduced test clocks for partial scan designs

Abstract: Partial scan design technique is often preferred to full scan because the use of smaller number of scan flip-flops leads to less performance degradation and less overhead. However, the number of clocks required to apply a test vector is proportional to the number of flip-flops in the scan path whenever scan is performed. This tends to increase the test application considerably. In this paper we presents an algorithm to generate a test with fewer test clocks for partial scan designs by using sequential test generation and scan strategies. The objective is to find a test that requires less test clocks while achieving high fault coverage. The algorithm, Test Application time Reduction for Partial scan design (TARP), is implemented and tested on a set of ISCAS sequential benchmark circuits. The algorithm produces a test with substantial reduction in the number of test clocks, compared to a test in which each test vector is associated with a scan operation. >

Hypergraph coloring and reconfigured RAM testing

Abstract: RAM decoders are designed with a view to minimize the overall silicon area and critical path lengths. This can result in designs in which-physically adjacent rows (and columns) are not logically adjacent. Even if physically adjacent rows (and columns) are logically adjacent, there are other issues that preclude the possibility of identical physical and logical addresses. State-of-the-art memory chips are designed with spare rows and spare columns for reconfiguration purposes. After a memory chip is reconfigured, physically adjacent cells may no longer have consecutive logical addresses. Test algorithms used at later stages for the detection of physical neighborhood pattern sensitive faults have to consider the fact that the address mapping of the memory chip is no longer available. We present test algorithms to detect 5-cell and 9-cell physical neighborhood pattern sensitive faults and arbitrary 3-coupling faults, even if the logical and physical addresses are different and the physical-to-logical address mapping is not available. These algorithms have test lengths of O(N[log/sub 3/N]/sup 4/) and O(N[log/sub 3/N]/sup 2/), respectively, for N-bit RAMs, and are especially suited for testing reconfigured DRAMs. They also detect other conventional faults such as stuck-at faults and decoder faults. These test algorithms are based on efficiently identifying all triplets of objects among a group of n objects. We formulated this triplet identification problem as a hypergraph coloring problem, and developed an efficient 3-coloring algorithm that colors the n vertices of a complete uniform hypergraph of rank 3 such that each edge of the hypergraph is trichromatically colored in at most [log/sub 3/n]/sup 2/ coloring steps. >

Behavioral synthesis of testable designs

Abstract: High-level synthesis tools automatically produce RTL designs from algorithmic specifications. These designs, however, are not necessarily easy to test. In this paper we present TBINET, an algorithm for module and register binding, which generates RTL designs having low testability overheads. It obtains a heuristic solution to the binding problem by mapping it onto a sequence of minimum cost network flow problems which can be solved very quickly. A cost function that considers the testability of the design is defined in the paper. The results of experiments on various benchmarks show that the designs produced by our binding algorithm are indeed easier to test as compared to circuits designed without testability considerations. >

An algorithm to test reconfigured RAMs

Abstract: State-of-the-art RAM chips are invariably reconfigurable. After reconfiguration, the logical neighborhood of the memory cells may no longer be same as the physical neighborhood. Test algorithms used after reconfiguration to detect physical neighborhood faults have to consider that (i) the physical and logical neighborhoods are different and (ii) the address mapping of the reconfigured RAM is no longer available. Another reason for distinct logical and physical neighborhoods is address line scrambling, done to minimize the silicon area and the critical path lengths. We present a test algorithm to detect 5-cell physical neighborhood pattern sensitive faults in reconfigured RAMs and RAMs with scrambled address lines. This algorithm is based on the widely used MSCAN and Marching tests, and requires only O(N upper bound/spl lsqb/log/sub 2/N/spl rsqb/) reads and writes to test an N-bit RAM. It also detects other faults such as stuck-at faults, decoder faults, 2-coupling faults, and 3-coupling faults. >

Testable synthesis and testing of finite state machines

Abstract: In this paper, me outline a method for testable synthesis of finite state machines (FSMs). We address the design for testability issue for testing FSMs with and without scan. The experimental results on the MCNC benchmarks show that our designs are 100% testable with small to moderate increase in area. >

On-chip testing of random access memories

Abstract: This article gives an overview of the Built-In Self-Test techniques for stand alone Random-Access Memory chips. It identifies the limitations of the existing fault models and the test algorithms used to test large RAMs. Methods to reduce test time for testing large RAMs are categorized. The article argues that even linear time test algorithms must use architecture and design for testability induced parallelisms to keep the total test time to an acceptable limit. Following that two algorithms are presented that can be used to test large RAMs for neighborhood pattern sensitive faults. Test lengths and test time for application of these algorithms are computed and it is suggested that a microprogrammed controller based scheme be used to implement self-test in stand alone RAMs.