Showing papers in "Journal of Electronic Testing in 1994"

Self-checking combinational circuit design for single and unidirectional multibit error

Abstract: This article presents novel input and output encoding techniques such that the resulting circuit is bidirectional error-free. The circuit can be fully optimized and any types of gates can be used. These schemes are used to design the functional part of a self-checking circuit. The input encoding algorithm can be applied to any circuit without significantly increasing the input lines. The output encoding technique involves graph-embedding which is done with heuristic method of polynomial complexity. The heuristic technique produces nearly optimal output encoding. Previously published work restrict the types of gates used in the circuit to non-inversion gates (AND/OR), and use inverters only at the inputs. The proposed techniques have a clear advantage over the currently available techniques because they allow the use of any types of gates. These techniques do not necessarily increase the overhead when applied to different MCNC benchmark circuits as the experimental results indicate. The only restriction is that either the inputs or the outputs have to be symbolic, and the two-level description of a circuit has to be given.

A class of two-dimensional cellular automata and their applications in random pattern testing

Abstract: A basic framework to characterize the behavior of two-dimensional (2-D) cellular automata (CA) has been proposed. The performance of the regular structure of the 2-D CA has been evaluated for pseudo-random pattern generation. The potential increase in the local neighborhood structure for 2-D CA has led to better randomness of the generated patterns as compared to LFSR and 1-D CA. The quality of the random patterns generated with 2-D CA based built-in-self-test (BIST) structure has been evaluated by comparing the fault coverage on several benchmark circuits. Also a method of synthesizing 2-D CAs to generate patterns of specified length has been reported. The patterns generated can serve as a very good source of random two-dimensional sequences and also variable length parallel pattern generation having virtually nil correlation among the bit patterns.

Tutorial on semiconductor memory testing

Abstract: This article is a tutorial introduction to the field of semiconductor memory testing. It begins by describing the structure and operation of the main types of semiconductor memory. The various ways in which manufacturing defects and failure mechanisms can cause erroneous memory behavior are then reviewed. Next we describe the different contexts in which memories are tested together with the corresponding different types of tests. The closely related processes of fault modeling and test development are then summarized. Various design for testability strategies for memories are also presented. Finally, current trends in the design and testing of memory are outlined.

Effective march algorithms for testing single-order addressed memories

Abstract: Today's commonly used macro generators provide for read/write memories of type SRAM, Register File, Multi-Port RAM, Single-Order Addressed Memory (e.g. FIFO), CAM (Content Addressable Memory), etc. In addition to automatically generating the required momory, the appropriate test, which may be applied externally or internally as a BIST, has to be determined. Current literature provides tests for most memory types; however, tests for single-order addressed (SOA) memories, whereby the address can only change in one direction (e.g. from address 0 ton-1) have not been published yet. SOA memories are used in FIFOs and in applications where the BIST area overhead and/or speed penalty for normal (dual) order addressing are not acceptable. This article illustrates the testing problems and presents a family of march algorithms optimized for testing SOA memories.

Deterministic tests for detecting single V -coupling faults in RAMs

Abstract: We consider the problem of detecting singleV-coupling faults (as defined by Nair, Thatte, and Abraham) inn×1 random-access memories (RAMs). First we derive a lower bound of 2 V−2 nlog2 n+(2 V +3)n on the length of any test that detects all singleV-coupling faults, for 2≤V≤47 andn=2 e whereeɛ{8,...,34}. In the derivation we make use of a family of binary codes which we call (n, θ)-exhaustive codes. We then describe a procedure which, given any (n, V−1)-exhaustive code, constructs a test that detects all singleV-coupling faults, forn≥V>2. Following this approach, optimal (n,1)- and (n, 2)-exhaustive codes are used to construct S2CTEST and S3CTEST, which are efficient tests of length 10n and 4nlog2 n+18n that detect all single 2- and 3-coupling faults, respectively. S3CTEST is roughly five times shorter, for current RAM capacities, than Papachristou and Sahgal's test of length 24n[log2 n]+n. Codes generated according to Tang and Chen are used similarly to construct S4CTEST and S5CTEST, which are tests of approximate length 8.6n(log2 n)1.585 and 9.6n(log2 n)2.322 that detect all single 4- and 5-coupling faults, respectively. S5CTEST has the interesting property of being able to detect all single physical neighborhood pattern-sensitive faults without requiring the mapping from logical cell addresses to physical cell locations. S5CTEST also detects the scrambled pattern-sensitive fault recently proposed by Franklin and Saluja; moreover, the new test is approximately fourteen times shorter (for 1 and 4 Mbit RAMs) than the test they describe.

High level test economics advisor (Hi-TEA)

Abstract: To produce high-quality and cost-effective multichip systems, they must be designed with test and fault diagnosis as critical design requirements. However, deciding on where and when to test and whether to apply Design For Test DFT) and Built-In Self-Test (BIST) at the IC, multichip module (MCM) or board level requires considerable study and evaluation to determine the economics of the various solutions and the payback. In this article we describe a tool called High Level Test Economics Advisor (Hi-TEA) that analyzes the economics of various test strategies for multichip designs at an early stage of the design cycle. The tool also allows the user to perform trade-off analysis on the impact of various cost, yield, or test effectiveness parameter on the final cost and quality of multichip designs. Experimental trade-off analysis data that were generated using the tool for some leading-edge multichip designs will also be presented.

Energy minimization and design for testability

Abstract: The problem of fault detection in general combinational circuits is NP-complete. The only previous result on identifying easily testable circuits is due to Fujiwara who gave a polynomial time algorithm for detecting any single stuck fault inK-bounded circuits. Such circuits may only contain logic blocks with no more thanK input lines and the blocks are so connected that there is no reconvergent fanout among them. We introduce a new class of combinational circuits called the (k, K)-circuits and present a polynomial time algorithm to detect any single or multiple stuck fault in such circuits. We represent the circuit as an undirected graphG with a vertex for each gate and an edge between a pair of vertices whenever the corresponding gates have a connection. For a (k, K)-circuit,G is a subgraph of ak-tree, which, by definition, cannot have a clique of size greater thank+1. Basically, this is a restriction on gate interconnections rather than on the function of gates comprising the circuit. The (k, K)-circuits are a generalization of Fujiwara'sK-bounded circuits. Using the bidirectional neural network model of the circuit and the energy function minimization formulation of the fault detection problem, we present a test generation algorithm for single and multiple faults in (k, K)-circuits. This polynomial time aggorithm minimizes the energy function by recursively eliminating the variables.

Design of a C-testable booth multiplier using a realistic fault model

Abstract: A Booth multiplier is the most widely used type of multiplier In this article, the testability issues involved in its design are discussed In contrast to previous work, the fault model includes not only node stuck-at faults, but also transistor stuck-open and stuck-close faults Moreover, as a result of adopting a hierarchical testability approach, the designed Booth multiplier turns out to be fully C-testable To achieve this C-testability, only three additional controllable inputs are required, which results in a negligible area and delay overhead

Test strategy planning using economic analysis

Abstract: This article will discuss the impact on testing of life-cycle costs and present an approach for minimizing the overall life-cycle costs of a product by selecting the most economic test strategy at each stage. The selection of test strategy is based on a detailed economic analysis of the different test techniques available.

Sensitivity analysis in economics based test strategy planning

Abstract: This article will present methods to analyze the sensitivity of test costs to the inaccuracy of the individual costing parameters. The results show that a few parameters—e.g., the gate count—need very detailed estimates, whereas the accuracy of many other parameters is insignificant in 99% of all cases. The techniques presented allow an in-depth evaluation of what is perceived as the main drawback in the use of economic modeling methods, namely, the element of risk associated with inaccuracies in the input data.

Improving quality: yield versus test coverage

Abstract: Until now, it has been thought that the best way to improve quality was to improve yield, that is, to improve the manufacturing process so that fewer defective parts are manufactured. This philosophy has been applied to all areas of manufacturing, from widgets to whalers. One of the tenets of this philosophy is that quality should not be tested in, but should be built in via a well-controlled process that is continuously improving. However, when it comes to semiconductors, significant improvements for a process in order to improve yields can cost millions of dollars. In such a capital intensive industry, where the life of a process is only a few years, such investments are often not in the best economic interests of a semiconductor manufacturer. How, then, can the customers’ requirements for quality be met? This article shows that for typical values of yield and test coverage, quality improves faster due to improvements in test coverage than it does for improvements in yield. As a result, testing can be used to achieve improvements in quality at lower costs, and therefore more economically, than improvements in the manufacturing process.

Trade-offs in scan path and BIST implementations for RAMs

Abstract: In this article we propose efficient scan path and BIST schemes for RAMs. Tools for automatic generation of these schemes have been implemented. They reduce the design effort and thus allow the designer to select the more appropriate scheme with respect to various constraints.

The economics of scan-path design for testability

Abstract: In this article, scan design for testability (DFT) methods are categorized based on the percentage of storage elements made scannable. The non-scan element state retention problem that occurs in partial scan design methods, in which not all of the storage elements are implemented as scan elements, is discussed. Solutions to this problem are described and the overheads associated with them are discussed. An economic model that allows the costs of a range of scan methods that differ in the percentage of storage elements made scannable to be compared with each other is presented. It is shown that, for systems produced in low volumes, the adoption of full scan DFT can be more cost-effective than partial scan DFT when life-cycle costs are considered if it results in significant reductions in the time taken to get the product to market.

A tale of two designs: the cheapest and the most economic

Abstract: Engineering economics is the study of how engineers choose to optimize their designs and construction methods to produce objects and systems that will optimize their efficiency and hence the satisfaction of their clients. We discuss some relevant concepts in engineering economics. We begin with the analysis of production and operational costs, and benefit-cost analysis and end with the economic arguments that justify design for testability.

Economic modeling of board test strategies

Abstract: A long and deep recession, coupled with continuous competitive pressure to reduce costs, is forcing many companies to review their test strategies. Testing costs have become a more significant proportion of the overall manufacturing cost even though manufacturing yields have increased dramatically over the past ten or twelve years. This causes attention to be focused on testing costs as a key source of cost reduction. The increased use of DFT and the integration of design and test are very positive moves towards controlling testing costs but other methods employed can often backfire. The increased use of low priced testers is one such method. The pressure to reduce costs, higher process yields and exhortations that “testing adds no value” can lead the test engineering manager to take the “cheap” route. In reality this can often turn out to be an expensive decision. The only way to avoid expensive mistakes is to perform an economic analysis of the alternative courses of action. In most cases this is done, but not always in the right manner or with the necessary amount of detail to make the comparisons meaningful. This article discusses the need for effective cost analysis of test strategies and highlights some of the pitfalls.

Measurement selection for parametric IC fault diagnosis

Abstract: This article presents experimental results which show feedforward neural networks are well-suited for analog IC fault diagnosis. Boundary band data (BBD) measurement selection is used to reduce the computational overhead of the FFN training phase. We compare the diagnostic accuracy between traditional statistical classifiers and feedforward neural networks trained with various measurement selection criteria. The feedforward networks consistently perform as well as or better than the other classifiers in term of accuracy. Training using BBD consistently reduces the FFN training efforts without degrading the performance. Experimental results suggest that feedforward networks provide a cost efficient method for IC fault diagnosis in a large scale production testing environment.

A test generation program for sequential circuits

Abstract: This article presents an automatic test pattern generation system based on both algebraic and topological techniques. Circuit partitioning, testability measures, 9-valued functions, pruning heuristics, and interactive fault simulation are employed to increase the performance of a modified version of the sequential D-Algorithm. Test generation results for someIscas'89 circuits are presented.

Cost based surface mount PCB design evaluation

Abstract: In today's manufacturing field there is continuous demand for product flexibility and shorter product throughput time. Production planning and cost estimating activities need to be speeded up. Consequently, the traditional gap between the designer who designs new products and the estimator who evaluates the financial consequences of the design is fading. Cost optimization is being integrated in the design process, and the designer needs to take more responsibility for the cost of the product at the design stage itself. There is a lack of tools to assist the designer in analyzing a Printed Circuit Board's (PCBs) design from a manufacturing perspective, especially from an economic aspect. This is true in Surface Mount Technology (SMT) production where the integration of the design and manufacturing functions is often hampered by the lack of sufficient, in-depth manufacturing knowledge and associated cost information. This research developed a cost estimation tool for the designer in the surface mount PCB assembly domain by integrating Computer Aided Design (CAD), Computer Aided Process Planning (CAPP), and cost estimation techniques using a knowledge based framework. Cost estimation can be done at two design stages. First, a rough cost estimate can be obtained from knowing the component mix, the type of boad material, and the size of board. Then, after the detailed design, a more accurate assembly cost can be obtained by generating a macro-process plan from the given CAD data. The cost module considers tangible factors including the material costs, the equipment costs, process costs, and the labor costs. The model used also considers the intangible cost in a preliminary evaluation of design costs. The cost advisor and the Design For Manufacture (DFM) environment have been developed using C++ and object oriented programming constructs under the MS Windows operating system.

Multichip systems trade-off analysis tool

Abstract: This article discusses the conceptual/specification phase of multichip system design. The automation of conceptual design practices will decrease design and manufacturing risks by allowing system designers to view the entire performance design space early in the design cycle prior to the initiation of traditional physical design activities.

Technology and layout-related testing of static random-access memories

Abstract: Static random-access memories (SRAMs) exhibit faults that are electrical in nature. Functional and electrical testing are performed to diagnose faulty operation. These tests are usually designed from simple fault models that describe the chip interface behavior without a thorough analysis of the chip layout and technology. However, there are certaintechnology and layout-related defects that are internal to the chip and are mostly time-dependent in nature. The resulting failures may or may not seriously degrade the input/output interface behavior. They may show up as electrical faults (such as a slow access fault) and/or functional faults (such as a pattern sensitive fault). However, these faults cannot be described properly with the functional fault models because these models do not take timing into account. Also, electrical fault models that describe merely the input/output interface behavior are inadequate to characterize every possible defect in the basic SRAM cell. Examples of faults produced by these defects are: (a) static data loss, (b) abnormally high currents drawn from the power supply, etc. Generating tests for such faults often requires a thorough understanding and analysis of the circuit technology and layout. In this article, we shall examine ways to characterize and test such faults. We shall divide such faults into two categories depending on the types of SRAMs they effect—silicon SRAMs and GaAs SRAMs.

Zero Aliasing ROM BIST

Abstract: Signature analyzers are very efficient output response compactors for BIST design The only limitation of signature analysis is the fault coverage reduction (aliasing) due to the information loss inherent to any data compaction In this article, in order to increase the effectiveness of ROM BIST, we take advantage from the simplicity of the error patterns generated by ROMs and we show that aliasing free signature analysis can be achieved in ROM BIST

Economics of “design for test” to remain competitive in the 90s

Abstract: This article emphasizes the criticality of maximizing “value adders” and minimizing the costs of “design for test” (DFT) in order to remain competitive in ASIC manufacturing in the 90s.

Fuzzy optimization models for analog test decisions

Abstract: Test decisions still constitute one of the most difficult and time-consuming design tasks. This is particularly true in the analog domain where some basic test questions have not yet been completely resolved. Since the gap between a good and a bad analog circuit is not always well-defined, extensive tests may result in the rejection of many fault-free ICs. The objective of this article is to propose fuzzy optimization models that can help in the more realistic formulation and resolution of the analog test problem. The set of good or fault-free ICs is considered as a fuzzy set. Each performance test is represented by a membership function. A global test measure is obtained by aggregating all the performance tests. An illustrative example using these concepts is provided.

Techniques for estimating test length under random test

Abstract: When a circuit is tested using random or pseudorandom patterns, it is essential to determine the amount of time (test length) required to test it adequately. We present a methodology for predicting different statistics of random pattern test length. While earlier methods allowed estimation only of upper bounds of test length and only for exhaustive fault coverage, the technique presented here is capable of providing estimates of all statistics of interest (including expected value and variance) for all coverage specifications.

Boundary scan in board manufacturing

Abstract: This article discusses the development of a board level manufacturing test for a surface mount board implemented with boundary scan. The board examined is a composite of several actual products. Methods for effectively developing a boundary scan test are examined along with some of the advantages of approaching the development in unique ways. Additionally, the criteria for using these methods are developed. Results for test development time and the resulting test coverage show that with two weeks of test development using boundary scan it is possible to increase the rate of solder opens detection from 80% to 99% for a large ball-grid-array module.

On-chip testing of random access memories

Abstract: This article gives an overview of the Built-In Self-Test techniques for stand alone Random-Access Memory chips. It identifies the limitations of the existing fault models and the test algorithms used to test large RAMs. Methods to reduce test time for testing large RAMs are categorized. The article argues that even linear time test algorithms must use architecture and design for testability induced parallelisms to keep the total test time to an acceptable limit. Following that two algorithms are presented that can be used to test large RAMs for neighborhood pattern sensitive faults. Test lengths and test time for application of these algorithms are computed and it is suggested that a microprogrammed controller based scheme be used to implement self-test in stand alone RAMs.

Comparing quality assurance methods and the resulting design strategies: experiences from complex designs

Abstract: Design quality assurance methods are compared in terms of cost and error detection efficiency using statistical data from several complex designs (Complexity>100.00 gates). A suitable strategy for error detection as a function of system complexity is identified, and the resulting design flow is described. The statistical control of the design process as a feedback loop to achieve error prevention is demonstrated. Using data from complex projects practical advice for managers is given.

On minimizing aliasing in scan-based compaction

Abstract: In this article we address the problem of compacting test response data captured in scan paths. We consider linear compactors, e.g., multiple-input signature registers, and the effect of their characteristic polynomials on the number of aliased faults. The novelty of our analysis lies in that it is based on a realistic error model which takes into account the time correlation among the errors in the test response data fed to the compactor. Such a correlation does exist in scan-based compaction, but has not been considered previously. Based on our analysis, we derive three conditions that should be satisfied to minimize aliasing. They impose little restriction on circuit design.

Trade-off analysis on cost and manufacturing technology of an electronic product: case study

Abstract: A trade-off analysis on the cost and system packaging metrics of an electronic product aimed at the commercial/retail industry has been carried out. By comparing the system cost and packaging metrics with those of comparable consumer products, we have determined that there is opportunity for significant cost, size, and weight reduction of the overall electronics packaging system. These include the use of fine pitch IC packages, smaller discrete components, denser PCB wiring technology, double sided IC package surface mount, surface mount connectors, and improved plastics for the product housing. The analysis concluded that PCB area reduction of 40%, using a single PCB instead of three boards, reduction in board cost of over 50% and product weight reduction of over 28% are possible using available technologies.

Self-test of sequential circuits with deterministic test pattern sequences

Abstract: This article describes a new approach for synthesizing a cost-efficient self-test hardware for a given set of deterministic test pattern sequences To minimize the test hardware effort instead of all the test sequences, only a very small subset will be selected such that a simple generation of all necessary test sequences will be ensured This procedure drastically decreases the storage requirements (about 80%) and therefore distinctly reduces the necessary test hardware overhead Experimental results on the ISCAS-S-benchmarks emphasize the efficiency of our approach