With multiple cores integrated on the same die, communication across cores is managed by on-chip interconnect called network-on-chip (NoC). Power and performance of these interconnect is a significant factor as the communication network consumes a considerable share of the power budget. In particular, the buffers used at every port of the NoC router consume considerable dynamic as well as static power. This paper attempts to reduce static power consumption by using non-volatile memory technology-based spin-transfer torque random access memory (STT-RAM) buffers. STT-RAM technology has the advantage of high density and low leakage but suffers from weaker write endurance. This impacts the lifetime of the router as a whole. The buffers in a router are allocated to virtual networks (VNets) and in-turn to virtual channels (VCs) within each VNet. To reduce uneven writes across the buffers, we propose policies to reduce intra-VNet write variation and inter-VNet write variation. The former performs write variation aware VC allocation in each VNet, and the latter does write variation aware buffer assignments to each VNet. Experimental evaluation on full system simulator shows that proposed policies reduce write variation to almost 0% and improve lifetime by 3.3 and 19.9 times for intra-VNet and inter-VNet, respectively. We also get significant gains in the energy delay product.

Write Variation Aware Buffer Assignment for Improved Lifetime of Non-Volatile Buffers in On-Chip Interconnects

Abstract Recently, non-volatile memory (NVM) technology has revolutionized the landscape of memory systems. With many advantages, such as non volatility and near zero standby power consumption, these byte-addressable memory technologies are taking the place of DRAMs. Nonetheless, they also present some limitations, such as limited write endurance, which hinders their widespread use in today’s systems. Furthermore, adjusting current data management systems to embrace these new memory technologies and all their potential is proving to be a nontrivial task. Because of this, a substantial amount of research has been done, from both the database community and the storage systems community, that tries to improve various aspects of NVMs to integrate these technologies into the memory hierarchy. In this work, which is the extended version of Kargar and Nawab (Proc. VLDB Endowment 14(12):3194–3197, 2021), we explore state-of-the-art work on deploying NVMs in database and storage systems communities and the ways their limitations are being handled within these communities. In particular, we focus on (1) the challenges that are related to high energy consumption, low write endurance and asymmetric read/write costs and (2) how these challenges can be solved using hardware and software solutions, especially by reducing the number of bit flips in write operations. We believe that this area has not gained enough attention in the data management community and this tutorial will provide information on how to integrate recent advances from the NVM storage community into existing and future data management systems. 

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Challenges and future directions for energy, latency, and lifetime improvements in NVMs

With the advancement in CMOS technology and multiple processors on the chip, communication across these cores is managed by a network-on-chip (NoC). Power and performance of these NoC interconnects have become a significant factor.The authors aim to reduce the leakage power consumption of NoC buffers by the use of non-volatile spin transfer torque random access memory (STT-RAM)-based buffers. STT-RAM technology has the advantages of high density and low leakage but suffers from low endurance. This low endurance has an impact on the lifetime of the router on the whole due to unwanted write-variations governed by virtual channel (VC) allocation policies. Here various VC allocation policies that help the uniform distribution of the writes across the buffers are proposed. Iso-capacity and iso-area-based alternatives to replace SRAM buffers with STT-RAM buffers are also presented. Pure STT-RAM buffers, however, impact the network latency. To mitigate this, a hybrid variant of the proposed policies which uses alternative VCs made of SRAM technology in the case of heavy network traffic is proposed. Experimental evaluation of full system simulation shows that proposed policies reduce the write variation by 99% and improve lifetime by 3.2 times and 1093 times, respectively. Also a 55.5% gain in the energy delay product is obtained.

https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cdt.2019.0039

Write-variation aware alternatives to replace SRAM buffers with non-volatile buffers in on-chip interconnects

In a multi-core system, communication across cores is managed by an on-chip interconnect called Network-on-Chip (NoC). The utilization of NoC results in limitations such as high communication delay and high network power consumption. The buffers of the NoC router consume a considerable amount of leakage power. This paper attempts to reduce leakage power consumption by using Non-Volatile Memory technology-based buffers. NVM technology has the advantage of higher density and low leakage but suffers from costly write operation, and weaker write endurance. These characteristics impact on the total network power consumption, network latency, and lifetime of the router as a whole.In this paper, we propose a write reduction technique, which is based on dirty flits present in write-back data packets. The method also suggests a dirty flit based Virtual Channel (VC) allocation technique that distributes writes in NVM technology-based VCs to improve the lifetime of NVM buffers.The experimental evaluation on the full system simulator shows that the proposed policy obtains a 53% reduction in write-back flits, which results in 27% lesser total network flit on average. All these results in a significant decrease in total and dynamic network power consumption. The policy also shows remarkable improvement in the lifetime.

DidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects

In the era of dark silicon, several components on the chip [i.e., cores, memory, and network on chip (NoC)] need to be powered-off or run in low-power mode. This is mainly due to the increased leakage power consumption at smaller technology nodes. Other than the power consumed by cores and caches, power and performance of the interconnects is a significant factor as the communication network consumes a considerable share of the power budget. In particular, the buffers used at every port of the NoC router consume considerable dynamic as well as static power. To support dark silicon and save energy, a popular approach is to power off the routers and wake them up when needed. However, this affects the packet latency, and we need to observe the traffic through the nodes to decide turning the routers ON–OFF. In this article, we propose to keep the routers always powered ON to maintain constant connectivity and investigate various approaches. One proposal is to frequency scale the routers connected to powered OFF nodes, and the other proposals are to use a combination of SRAM and nonvolatile spin-transfer torque random access memory-based VCs in the routers. By managing which VCs to be active at a given time, we achieve energy savings. The proposals are evaluated by varying the percentage of dark nodes on the chip. The experimental results show that all proposals yield significant energy savings while maintaining connectivity.

Investigating Frequency Scaling, Nonvolatile, and Hybrid Memory Technologies for On-Chip Routers to Support the Era of Dark Silicon

Recent advances in CMOS technology adds more transistors to the chip that are utilised for improving processing capability by adding multiple processing components. These multiple cores raise the data demands leading to larger on-chip caches. Together, these add to the energy consumption as well as heat dissipation. Increase in chip temperature requires efficient cooling mechanisms as high temperatures can damage the onchip circuitry. Thus, the performance enhancement comes at the cost of higher power budget as well as temperature. Large onchip caches occupy significant area of the chip and are major contributors to leakage energy. It is known that as technology scales leakage becomes a prominent component which also affects the chip temperature. This paper aims to control the chip temperature by controlling the leakage energy dissipated by the last level caches (LLCs). Towards this we propose a hybrid LLC that uses a combination of SRAM cache banks and non-volatile memory (NVM) technology based STT-RAM banks. STT-RAM technology has the advantage of high density and low leakage.We demonstrate that low-leakage STT-RAM banks help in reducing the temperature of the tile in which they are located and it also assists in reducing the average chip temperature. Experimental evaluation on an isoarea and iso-capacity architecture that uses a hybrid LLC shows reduction the average chip temperature as well as gives gains in static energy and EDP compared to baseline architecture.

Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors

The era of dark silicon demands that several components on the chip (i.e. cores, memory and NoC) need to be powered-off or run in low-power mode. This is mainly due to the increased leakage power consumption at smaller technology nodes. Even when core components are turned-off the communication network is expected to maintain connectivity. Therefore the challenge shifts to designing NoC with low power consumption with a reasonable throughput. NoC router power consumption can be controlled by powering-off the router when idle and waking it when traffic arrives. However, in such approaches, the wake-up cycles add to the packet latency affecting the performance. It has been observed that buffers in a router are the main contributors to leakage. In this paper, we attempt to reduce leakage power of network-on-chip by keeping the routers powered on, but keeping most of the buffers in the powered-off state. In the context of dark silicon, for the routers attached to the gated cores, we keep most of the buffers powered-off saving their leakage energy. In order to maintain connectivity, we keep a minimal number of buffers powered-on that help in traffic management without adverse effect on the performance. Experimental evaluation shows significant savings in leakage energy with the marginal performance penalty. Results are shown in comparison to a baseline using no power gating and with another existing policy.

Khushboo Rani

Papers

Write Variation Aware Buffer Assignment for Improved Lifetime of Non-Volatile Buffers in On-Chip Interconnects

Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors

Write-variation aware alternatives to replace SRAM buffers with non-volatile buffers in on-chip interconnects

DidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects

Non-blocking Gated Buffers for Energy Efficient on-chip Interconnects in the era of Dark Silicon