An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

A Three Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers (103) such that each layer may be separately optimized. One control logic circuit (101) suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory (100) involves thinning of the memory circuit (103) to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Three dimensional structure memory

Process gas discharged from a bypass pipe to a gas exhaust system can be prevented from diffusing back to the inside of a process chamber without having to install a dedicated vacuum pump at the downstream side of the bypass pipe. The substrate processing apparatus includes a process chamber accommodating a substrate, a gas supply system supplying process gas from a process gas source to the process chamber for processing the substrate, a gas exhaust system configured to exhaust the process chamber, two or more vacuum pumps installed in series at the gas exhaust system, and a bypass pipe connected between the gas supply system and the gas exhaust system. The most upstream one of the vacuum pumps is a mechanical booster pump, and the bypass pipe is connected between the mechanical booster pump and the rest vacuum pumps located at a downstream side of the mechanical booster pump.

Substrate Processing Apparatus

A method of separating a thin film of GaN epitaxially grown on a sapphire substrate. The thin film is bonded to an acceptor substrate, and the sapphire substrate is laser irradiated with a scanned beam at a wavelength at which sapphire is transparent but the GaN is strongly absorbing, e.g., 248 nm. After the laser irradiation, the sample is heated above the melting point of gallium, i.e., above 30° C., and the acceptor substrate and attached GaN thin film are removed from the sapphire growth substrate. If the acceptor substrate is flexible, the GaN thin film can be scribed along cleavage planes of the GaN, and, when the flexible substrate is bent, the GaN film cleaves on those planes. Thereby, GaN lasers and other electronic and opto-electronic devices can be formed.

Separation of thin films from transparent substrates by selective optical processing

A dielectric film containing LaAlO 3 and method of fabricating a dielectric film contained LaAlO 3 produce a reliable gate dielectric having a thinner equivalent oxide thickness than attainable using SiO 2 . The LaAlO 3 gate dielectrics formed are thermodynamically stable such that these gate dielectrics will have minimal reactions with a silicon substrate or other structures during processing. A LaAlO 3 gate dielectric is formed by atomic layer deposition employing a lanthanum sequence and an aluminum sequence. A lanthanum sequence uses La(thd) 3 (thd=2,2,6,6-tetramethl-3,5-heptanedione) and ozone. An aluminum sequence uses either trimethylaluminium, Al(CH 3 ) 3 , or DMEAA, an adduct of alane (AlH 3 ) and dimethylehtylamine [N(CH 3 ) 2 (C 2 H 5 )], with distilled water vapor.

Atomic layer-deposited laaio3 films for gate dielectrics

Dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO 2 . Forming a layer of hafnium oxide by atomic layer deposition and forming a layer of a lanthanide oxide by electron beam evaporation, where the layer of hafnium oxide is adjacent and in contact with the layer of lanthanide, provides a dielectric layer with a relatively high dielectric constant as compared with silicon oxide. The dielectric can be formed as a nanolaminate of hafnium oxide and a lanthanide oxide.

Lanthanide oxide / hafnium oxide dielectric layers

An improved structure and method are provided for increasing the operational bandwidth between different circuit devices, e.g. logic and memory chips, without requiring changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can consist of recycled rejected wafers from the front-end semiconductor processing. Micro-machined vias are formed through the silicon interposer. The micro-machined vias include electrical contacts which couple various integrated circuit devices located on the opposing surfaces of the silicon interposer.

Structure and method for a high performance electronic packaging assembly

An integrated circuit and fabrication method includes a memory cell for a dynamic random access memory (DRAM). Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried first and second gates are provided for each access transistor on opposing sides of the pillars. Buried word lines extend in trenches orthogonal to the bit lines. The buried word lines interconnect ones of the first and second gates. In one embodiment, unitary gates are interposed and shared between adjacent pillars for gating the transistors therein. In another embodiment, separate split gates are interposed between and provided to the adjacent pillars for separately gating the transistors therein. In one embodiment, the memory cell has a surface area that is approximately 4 F 2 , where F is a minimum feature size. Bulk-semiconductor and semiconductor-on-insulator (SOI) embodiments are provided.

Memory cell having a vertical transistor with buried source/drain and dual gates

The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ) and tin oxide (SnO 2 ) acting as a single dielectric layer with a formula of Zr X Hf Y Sn 1-X-Y O 2 , and a method of fabricating such a dielectric layer is described that produces a reliable structure with a high dielectric constant (high k). The dielectric structure is formed by depositing zirconium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing hafnium oxide onto the substrate using precursor chemicals, followed by depositing tin oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric may be used as a gate insulator, a capacitor dielectric, or as a tunnel insulator in non-volatile memories, because the high dielectric constant (high k) provides the functionality of a much thinner silicon dioxide film.

Kie Y. Ahn

Papers

Atomic layer-deposited laaio3 films for gate dielectrics

Lanthanide oxide / hafnium oxide dielectric layers

Structure and method for a high performance electronic packaging assembly

Memory cell having a vertical transistor with buried source/drain and dual gates

ATOMIC LAYER DEPOSITION OF Zrx Hfy Sn1-x-y O2 FILMS AS HIGH k GATE DIELECTRICS