A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.

Integrated circuit and method of designing layout of integrated circuit

An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically connected together.

Integrated circuit and semiconductor device

The invention provides a reservation method for medical examination items, a medium, terminal equipment and a system. The method comprises the following steps: obtaining examination item information of a patient, wherein the examination item information comprises examined items and items to be examined; obtaining a characteristic parameter of each examination item, and determining whether conflicting examination items exist in the items to be examined according to the characteristic parameter of each inspection item; and, if the conflicting examination items exist, adjusting an examination time sequence of the items to be examined according to an reservation instruction of the patient. According to the method, optimal allocation of hospital resources is achieved through the reasonable timesequence adjustment when a conflict exists between examination items reserved by the patient, and the waiting time of the patient is effectively shortened.

Reservation method for medical examination items, medium, terminal equipment and system

A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

Semiconductor device including standard cells

A computer-implemented method includes placing standard cells based on design data defining an integrated circuit. A layout of the integrated circuit is generated by performing colorless routing. First, second, third and fourth patterns included in a quadruple patterning lithography (QPL) layer are arranged, based on space constraints, on the placed standard cells. The generated layout is stored to a computer-readable storage medium. The space constraints define minimum spaces between the first, second, third and fourth patterns. The method includes assigning first, second, third and fourth colors to the first, second, third and fourth patterns, respectively. Masks are generated based on the layout. A semiconductor device is manufactured by using the generated masks. A space between two patterns of the first, second, third and fourth patterns smaller than a corresponding space constraint of the space constraints indicates a color violation.

Integrated circuit for quadruple patterning lithography, and computing system and computer-implemented method for designing integrated circuit

A computer-implemented method of designing an integrated circuit (IC) includes allocating a plurality of colors to a plurality of patterns corresponding to one layer of a first cell so that a multi-patterning technology is designated for use in forming the plurality of patterns, the first cell being a multi-height cell corresponding to a plurality of rows, generating a plurality of shift cells, in which a color remapping operation associated with the plurality of patterns is performed for each row, with respect to the first cell, and storing a cell set including the first cell and the plurality of shift cells in a standard cell library.

Integrated circuit and method of designing integrated circuit

To improve space efficiency, a scan flip flop according to the present disclosure includes: an input part which selects any one of a data input signal and a scan input signal according to an operation mode and provides it as an internal signal; and a flip flop which has a cross couple structure which includes a first and a second tri-state inverters sharing a first output node and facing each other, and latches the internal signal according to a clock signal.

Scan flop flop and scan test circuit including the scan flip flip

According to one aspect of a technical idea of the present invention, an integrated circuit capable of providing enhanced durability may comprise: a first conductive pattern formed at a first conductive layer; a second conductive pattern formatted at a second conductive layer on the first conductive layer; and a via which is electrically coupled to the first and second conductive patterns and in which a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern respectively pass through the via at different times The via may be disposed on the first conductive pattern so that a path of the first current and a path of the second current do not overlap each other in the first conductive pattern

Integrated circuit including interconnection for mitigating electromigration and method for fabricating the same

An apparatus and method for supporting a medical examination based on a personalized checklist. The apparatus includes a checklist generator to generate a personalized checklist based on a patient's medical information; and an item performance confirmer to determine whether each item included in the checklist is performed by analyzing a medical examination process of the patient.

Kim Ha Young

Papers

Integrated circuit and method of designing integrated circuit

Scan flop flop and scan test circuit including the scan flip flip

Integrated circuit including interconnection for mitigating electromigration and method for fabricating the same

Apparatus and method for supporting medical examination based on personalized checklist