A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.

Materials, systems and methods for optoelectronic devices

Temporal noise sets the fundamental limit on image sensor performance, especially under low illumination and in video applications. In a CCD image sensor, temporal noise is primarily due to the photodetector shot noise and the output amplifier thermal and 1/f noise. CMOS image sensors suffer from higher noise than CCDs due to the additional pixel and column amplifier transistor thermal and 1/f noise. Noise analysis is further complicated by the time-varying circuit models, the fact that the reset transistor operates in subthreshold during reset, and the nonlinearity of the charge to voltage conversion, which is becoming more pronounced as CMOS technology scales. The paper presents a detailed and rigorous analysis of temporal noise due to thermal and shot noise sources in CMOS active pixel sensor (APS) that takes into consideration these complicating factors. Performing time-domain analysis, instead of the more traditional frequency-domain analysis, we find that the reset noise power due to thermal noise is at most half of its commonly quoted kT/C value. This result is corroborated by several published experimental data including data presented in this paper. The lower reset noise, however, comes at the expense of image lag. We find that alternative reset methods such as overdriving the reset transistor gate or using a pMOS transistor can alleviate lag, but at the expense of doubling the reset noise power. We propose a new reset method that alleviates lag without increasing reset noise.

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Analysis of temporal noise in CMOS photodiode active pixel sensor

An imager with dual conversion gain floating diffusion regions. The dual conversion gain regions yield (1) high conversion gain and sensitivity to achieve excellent low light performance and (2) high full well capacity and conversion gain to achieve high dynamic range. A dual conversion gain element is coupled between each floating diffusion node and a respective capacitor. The dual conversion gain element switches in the capacitance of the capacitor to change the conversion gain of the floating diffusion node from a first conversion gain to a second conversion gain. The imager may be a CMOS or CCD type imager.

Dual conversion gain imagers

Fixed pattern noise (FPN) for a CCD sensor is modeled as a sample of a spatial white noise process. This model is, however, not adequate for characterizing FPN in CMOS sensors, since the redout circuitry of CMOS sensors and CCDs are very different. The paper presents a model for CMOS FPN as the sum of two components: a column and a pixel component. Each component is modeled by a first order isotropic autoregressive random process, and each component. Each component is modeled by a first order isotropic autoregressive random process, and each component is assumed to be uncorrelated with the other. The parameters of the processes characterize each component of the FPN and the correlations between neighboring pixels and neighboring columns for a batch of sensor. We show how to estimate the model parameters from a set of measurements, and report estimates for 64 X 64 passive pixel sensor (PPS) and active pixel sensor (APS) test structures implemented in a 0.35 micron CMOS process. High spatial correlations between pixel components were measured for the PPS structures, and between the column components in both PPS and APS. The APS pixel components were uncorrelated.

/pdf/modeling-and-estimation-of-fpn-components-in-cmos-image-384f3ca5gf.pdf

Modeling and estimation of FPN components in CMOS image sensors

Following the trend of increased integration in complementary metal oxide semiconductor (CMOS) image sensors, we have explored the potential of implementing light filters by using patterned metal layers placed on top of each pixel’s photodetector. To demonstrate wavelength selectivity, we designed and prototyped integrated color pixels in a standard 0.18-µm CMOS technology. Transmittance of several one-dimensional (1D) and two-dimensional (2D) patterned metal layers was measured under various illumination conditions and found to exhibit wavelength selectivity in the visible range. We performed (a) wave optics simulations to predict the spectral responsivity of an uncovered reference pixel and (b) numerical electromagnetic simulations with a 2D finite-difference time-domain method to predict transmittances through 1D patterned metal layers. We found good agreement in both cases. Finally, we used simulations to predict the transmittance for more elaborate designs.

/pdf/integrated-color-pixels-in-0-18-microm-complementary-metal-2xf8v541a5.pdf

Integrated color pixels in 0.18-microm complementary metal oxide semiconductor technology.

An active pixel sensor. The active pixel sensor includes a photo-diode. The photo-diode conducting charge as a function of the intensity of light received by the photo-diode. The photo-diode includes a diode capacitance which collects charge conducted by the photo-diode which generates a photo-diode voltage. A switched capacitor is connected in parallel with the photo-diode when the photo-diode voltage drops below a pre-determined voltage potential. A capacitance of the switched capacitor adds to the diode capacitance when the switched capacitor is connected. The switched capacitor can be a gate capacitor. The active pixel sensor further includes electronic circuitry to allow a controller to sample the photo-diode voltage.

Adjustable gain active pixel sensor

A salient integration mode active pixel sensor. The active pixel sensor includes an amplify/compare transistor which has a threshold voltage. The amplify/compare transistor couples an input of the amplify/compare transistor to an output of the amplify/compare transistor when the input of the amplify/compare transistor exceeds the threshold voltage. A photo-diode generates a signal voltage which has a voltage level dependent upon the intensity of light received by the photo-diode. The signal voltage is coupled to the input of the amplify/compare transistor. A reset element couples a reset line to the photo-diode and discharges the photo-diode when the reset line is active. A coupling capacitor for couples a select line to the input of the amplify/compare transistor. The select line causes the input to the amplify/compare transistor to exceed the threshold voltage and thereby couple the signal voltage to the output of the amplify/compare transistor. The amplify/compare transistor can be an N-type MOSFET and the reset transistor can be an N-type MOSFET. Further, a back gate of the amplify/compare transistor is generally connected to a circuit ground.

Salient integration mode active pixel sensor

A MOSFET structure characterized by a lightly doped tip region located between the channel and drain, and a buried region located below the tip region and shifted laterally towards the drain. The buried region, which is doped to a level intermediate between that of the tip region and the drain, causes the channel current to deflect downwardly from the field oxide, through the lightly doped tip region, and into the buried region. The gradual electric field gradient produced by the structure and the deflection of the channel current away from the thin oxide greatly reduces the device's sensitivity to the hot electron effect. The method of the invention includes forming the lightly doped tip region, forming a first oxide spacer, forming the buried region, widening the oxide spacer, and finally forming the drain region.

Method for making an LDD MOSFET with a shifted buried layer and a blocking region

The time dependence of hot carrier degradation of n-channel MOSFETs and the methodology of accelerated stress have been investigated in detail. The time (T) dependence is found to be inconsistent with the simple expression of TN (N-0.25), but rather show a slow-down of the degradation rate. The slope of the degradation curve is also found to be dependent on the stress bias voltage. The projection of device lifetime by accelerated stress based on the TN law and the assumption of constant slope independent of stress bias is unreliable.

Kit M Cham

Papers

Adjustable gain active pixel sensor

Salient integration mode active pixel sensor

Method for making an LDD MOSFET with a shifted buried layer and a blocking region

Self-Limiting Behavior of Hot Carrier Degradation and Its Implication on the Validity of Lifetime Extraction by Accelerated Stress

MOSFET structure and method for making same