P
Paul Vande Voorde
Researcher at Hewlett-Packard
Publications - 23
Citations - 250
Paul Vande Voorde is an academic researcher from Hewlett-Packard. The author has contributed to research in topics: Leakage (electronics) & Trench. The author has an hindex of 8, co-authored 23 publications receiving 248 citations. Previous affiliations of Paul Vande Voorde include Avago Technologies.
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Patent
Method for producing recessed field oxide with improved sidewall characteristics
TL;DR: In this article, a method for producing field oxide in a silicon substrate by forming a thin oxide layer over the surface of the substrate, forming a thick oxide over the thin nitride layer, form a thick nitride layers over the thick oxide layer, patterning all four of the layers to espose the surface where the field oxide is to be formed, and growing the field oxides is described.
Patent
Method for making an LDD MOSFET with a shifted buried layer and a blocking region
Kit M Cham,Paul Vande Voorde +1 more
TL;DR: In this article, a MOSFET structure characterized by a lightly doped tip region located between the channel and drain, and a buried region located below the tip region and shifted laterally towards the drain was proposed.
Proceedings ArticleDOI
Self-Limiting Behavior of Hot Carrier Degradation and Its Implication on the Validity of Lifetime Extraction by Accelerated Stress
TL;DR: In this article, the authors investigated the time dependence of hot carrier degradation of n-channel MOSFETs and the methodology of accelerated stress and found that the time (T) dependence is inconsistent with the simple expression of the TN (N-0.25), but rather show a slowdown of the degradation rate.
Patent
Process of making a bipolar transistor with a trench-isolated emitter
TL;DR: In this article, a self-aligned trench-isolated emitter structure and the method for forming same is described, which can be either N-P-N type or P-N-P type depending on the materials of fabrication.
Patent
Method and apparatus for building up large scale on chip de-coupling capacitor on standard CMOS/SOI technology
Joseph Ku,Paul Vande Voorde +1 more
TL;DR: In this paper, the authors proposed a design scheme which could utilize virtually unused area to build efficient de-coupling capacitors without introducing additional manufacture cost, which is especially effective when the VLSI technology is scaled down further.