Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.

Methods and apparatus of stacking DRAMs

This paper describes low-voltage random-access memory (RAM) cells and peripheral circuits for standalone and embedded RAMs, focusing on stable operation and reduced subthreshold current in standby and active modes. First, technology trends in low-voltage dynamic RAMs (DRAMs) and static RAMs (SRAMs) are reviewed and the challenges of low-voltage RAMs in terms of cell signal charge are clarified, including the necessary threshold voltage, VT, and its variations in the MOS field-effect transistors (MOSFETs) of RAM cells and sense amplifiers, leakage currents (subthreshold current and gate-tunnel current), and speed variations resulting from design parameter variations. Second, developments in conventional RAM cells and emerging cells, such as DRAM gain cells and leakage-immune SRAM cells, are discussed from the viewpoints of cell area, operating voltage, and leakage currents of MOSFETs. Third, the concepts proposed to date to reduce subthreshold current and the advantages of RAMs with respect to reducing the subthreshold current are summarized, including their applications to RAM circuits to reduce the current in standby and active modes, exemplified by DRAMs. After this, design issues in other peripheral circuits, such as sense amplifiers and low-voltage supporting circuits, are discussed, as are power management to suppress speed variations and reduce the power of power-aware systems, and testing. Finally, future prospects based on the above discussion are examined.

Review and future prospects of low-voltage RAM circuits

A memory module includes a plurality of memory devices and a circuit. Each memory device has a corresponding load. The circuit is electrically coupled to the plurality of memory devices and is configured to be electrically coupled to a memory controller of a computer system. The circuit selectively isolates one or more of the loads of the memory devices from the computer system. The circuit comprises logic which translates between a system memory domain of the computer system and a physical memory domain of the memory module.

Memory module with a circuit providing load isolation and memory domain translation

A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Configurable memory circuit system and method

A memory circuit system and method are provided. In one embodiment, an interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits. In another embodiment, an interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits. In yet another embodiment, at least one memory stack comprises a plurality of DRAM integrated circuits. Further, a buffer circuit, coupled to a host system, is utilized for interfacing the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system. In still yet another embodiment, at least one memory stack comprises a plurality of DRAM integrated circuits. Further, an interface circuit, coupled to a host system, is utilized for interfacing the memory stack to the host system so to operate the memory stack as a single DRAM integrated circuit.

Memory circuit system and method

A semiconductor memory device includes in its chip a decoder circuit which receives external selection signals for selecting a memory chip. The decoder circuit performs the selection of the memory chip in accordance with a logic corresponding to the combination of the external selection signals. The selection logic can be changed by the user of the semiconductor device.

Semiconductor memory device with decoder for chip selection/write in

The present invention discloses a memory cell layout of a dynamic RAM of a folded bit line type MOS FET wherein the bit line pairs are extended in parallel away from the sense amplifiers. The present invention includes a particular bit line pair and at least one bit line of an adjacent bit line pairs positioned between the particular bit line pair and makes the capacitor regions corresponding to the mutually adjacent bit lines interleave and thereby improves the area efficiency of the capacitor region.

DRAM with interleaved folded bit lines

pads in the center of the chip, permit assembly within a 300mil 18 pin plastic DIP and 300mil26 pin plastic Small Outline J-lead package (SOJ). The cell structure is shown in Figure 1. First layer polycide forms the wordline. The second layer poly-Si, which forms the storage node, is extended over its own wordline and the next wordline. The third layer poly-Si, which forms the cell plate, is spread over the second layer poly-Si. The cell capacitor is formed between the second and third layer poly-Si. Bitline is formed by AI. Since the capacitor is formed over the wordlines, the address The chip layout, with peripheral circuitry and some of the

http://ieeexplore.ieee.org/iel6/8300/25932/01156775.pdf

A 1Mb DRAM with 3-dimensional stacked capacitor cells

A lower member of a cross wire structure formed in a semiconductor device, such as an MIS type semiconductor memory device, is provided with a structure of at least two layers of an impurity-containing polycrystalline semiconductor material according to the method disclosed. These layers are connected in parallel and their resistance is thus decreased. Furthermore, since these layers may be formed within insulating films over a semiconductor substrate, the degree of integration of the semiconductor device may be enhanced. The method for producing the cross electrodes allows simultaneous fabrication of other semiconductor devices, for instance MIS devices with components commonly fabricated with the cross electrode structures.

Semiconductor device having cross wires

PURPOSE:To enable the high speed write-in and prevention of mis-readout, by providing the memory cell formed with FET and a capacitor at the specified cross point for two sets of bit lines and two sets of word lines, and by differential amplification of signal between two sets of bit lines. CONSTITUTION:The memory cells consisting of static capacitors 1161, 1162 and MISFET1151, 1152 are respectively provided at the cross points of the line 104 and line 1171 and of the lines 105 and 1172 among two sets of parallel bit lines 104, 105 to which the differential type sense amplifier 101 is connected, and among two sets of word lines 1171, 1172, and the capacitor 1161 is selected via the word line 1171. Then, when the input amplifier 113 is connected by turning on MISFET106, 107 on the lines 104, 105, the lines 104, 105 are respectively at high and low potential, and the potential on the line 104 is increased with the amplifier 101 and the write- in to the capacitor 1161 can be ensured in high speed. This is the same to readout, and when the ground terminal 121 of the amplifier 101 is kept at low potential, the readout data is amplified, and it is further amplified at the amplifier 114 to prevent the production of mis-readout.

Kiyoshi Miyasaka

Papers

Semiconductor memory device with decoder for chip selection/write in

DRAM with interleaved folded bit lines

A 1Mb DRAM with 3-dimensional stacked capacitor cells

Semiconductor device having cross wires

Semiconductor memory unit