An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Flash EEprom system

The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16 , 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices (15, 16 or 17), where the control information includes device-select information and the bus (18) has substantially fewer bus lines than the number of bits in a single address, and the bus (18) carries device-select information without the need for separated device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus (18) and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices (15, 16, 17). The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an Address Valid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Integrated circuit I/O using a high performance bus interface

In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored. The storage system includes a memory controller coupled to the host; and a nonvolatile memory bank coupled to the memory controller via a memory bus, the memory bank being included in a non-volatile semiconductor memory unit, the memory bank has storage blocks each of which includes a first row-portion located in said memory unit, and a corresponding second row-portion located in each of the memory unit, each of the memory row-portions provides storage space for two of said sectors, wherein the speed of performing write operations is increased by writing sector information to the memory unit simultaneously.

Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices

A method and apparatus for transferring data between two storage media, and is used in an illustrative embodiment to transfer data between two storage media in a shadow set, the storage media being accessible to one or more host processors. The method of the preferred embodiment includes the steps of: A. receiving a command from one of the host processors, the command specifying data to be transferred from a first storage medium to a second storage medium; B. transferring the data specified in the command received from the host from the first storage medium to the second storage medium in a series of subtransfers, each of the subtransfers transferring a portion of the data; and C. processing one or more I/O requests to the shadow set received from one or more host processors by, for each received I/O request: a. implementing the I/O request if the I/O request does not involve a section of the shadow set currently involved in one of the subtransfers; and b. stalling the I/O request if the I/O request involves a section of said shadow set currently involved in one of the subtransfers, and implementing the I/O request when the subtransfer has completed.

Transferring data in a digital data processing system

Semiconductor memory device having error correction function and incorporating redundancy configuration

A semiconductor memory (DRAM) device comprises memory cells, each of which is composed of an FET and a capacitor. The FET has an SOI structure. The capacitor is composed of a dielectric layer as an insulating layer for the SOI structure, an upper capacitor electrode as a semiconductor layer for the SOI structure, and a lower capacitor electrode as a semiconductor substrate. The substrate is biased with a voltage at an intermediate level between a first storage voltage and a second storage voltage.

Semiconductor memory device formed of a SOI-type transistor and a capacitor

In a semiconductor memory device having stacked capacitor-type memory cells, the capacitor of each memory cell comprises an electrode, an insulating layer, and a counter electrode. The electrode is connected electrically to a source or drain region of a transfer transistor and extends over a part of a word line adjacent to another word line serving a gate electrode of the transfer transistor, at which part no memory cell is formed.

Semiconductor memory device having stacked capacitor- type memory cells

( A random access memory (DRAM) device formed on a semiconductor substrate having an array of memory cells (MC) which are divided in several sub-arrays (MCA 0 .. 3). The device has memory blocks each containing one of the subarrays, a word decoder (WDO .. 3) and column decoder (CDO .. 3). Each of the memory blocks (MC) is selected independently to perform an access operation and refresh operation. As long as different memory blocks (MC) are selected for respective operations, the both operations are performed in paralle, however when the same memory block (MC) is selected for both operations, namely double selected, a comparison circuit (43) detects the double selection and the priority to one of both operations are determined and perform the operation selected preferentially. Usually, the refresh oriented operation is allowed. However, in order to decrease 'busy ratio' of the device, the refresh access operations is performed preferentially. Further complicated operation for priority selection, is performed according to a predetermined schedule memorized in a priority providing means (46, 48). In addition, a common word bus line (CWLi) is proposed for accessing each memory blocks, namely each sub-arrays, in order to reduce common word lines for realizing a further high packing density of the DRAM device. This common bus line is also applicable to other device such as a static RAM.

Random access memory device formed on a semiconductor substrate having an array of memory cells divided in sub-arrays

A semiconductor memory device has fuses coated with a protecting layer. The protecting layer is selectively etched to open windows so as to expose narrow center portions of the fuses. After the opening of the center windows, the fusing operation of the fuses is carried out to open a gap in the center window portion of the fuse material. In a preferred embodiment, another protective layer is then added to fill the gaps in the blown fuses.

Yoshihiro Takemae

Papers

Semiconductor memory device having error correction function and incorporating redundancy configuration

Semiconductor memory device formed of a SOI-type transistor and a capacitor

Semiconductor memory device having stacked capacitor- type memory cells

Random access memory device formed on a semiconductor substrate having an array of memory cells divided in sub-arrays

Semiconductor devices having fuses