An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

In electronic displays or imaging units, the control of pixels is achieved by an array of transistors. These transistors are in a thin film form and arranged in a two-dimensional configuration to form switching circuits, driving circuits or even read-out circuits. In this invention, thin film transistors and circuits with indium oxide-based channel layers are provided. These thin film transistors and circuits may be fabricated at low temperatures on various substrates and with high charge carrier mobilities. In addition to conventional rigid substrates, the present thin film transistors and circuits are particularly suited for the fabrication on flexible and transparent substrates for electronic display and imaging applications. Methods for the fabrication of the thin film transistors with indium oxide-based channels are provided.

Indium oxide-based thin film transistors and circuits

We present an overview of negative bias temperature instability (NBTI) commonly observed in p-channel metal–oxide–semiconductor field-effect transistors when stressed with negative gate voltages at elevated temperatures. We discuss the results of such stress on device and circuit performance and review interface traps and oxide charges, their origin, present understanding, and changes due to NBTI. Next we discuss the effects of varying parameters (hydrogen, deuterium, nitrogen, nitride, water, fluorine, boron, gate material, holes, temperature, electric field, and gate length) on NBTI. We conclude with the present understanding of NBTI and its minimization.

Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

https://engineering.purdue.edu/~ee650/downloads/NBTI-Ref1.pdf

A comprehensive model of PMOS NBTI degradation

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Memory Systems: Cache, DRAM, Disk

This paper presents a new reliability scaling scenario for CMOS devices with direct-tunneling ultra-thin gate oxide. Device degradation due to bias-temperature instability (BTI) was studied. First, the stress voltage dependence of BTI results indicate that the direct-tunneling electron and/or hole transport does not play a major role in the degradation mechanism. Secondly, it was found that the threshold voltage change caused by BTI for the PMOSFET limits the device lifetime, which is shorter than that defined by hot-carrier induced degradation for the NMOSFET. It originates from the difference of supply voltage dependence between BTI and hot-carrier degradation.

The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling

We investigated the degradation of device reliability due to Negative Bias Temperature Instability (NBTI) of PMOSFET with ultrathin gate oxide. It was experimentally demonstrated that the chemical reactions at the gate oxide/substrate interface and/or diffusion of hydrogen related species are the major cause of the NBTI. We also found that nitridation of gate oxide enhances NBTI. In order to suppress the NBTI, the density of hydrogen terminated silicon bond at the interface needs to be minimized. Thus, the concentration of nitrogen in thin gate oxide has to be optimized in terms of the reliability reduction due to NBTI.

NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-/spl mu/m gate CMOS generation

New analysis methods useful for understanding both complex waveforms and statistical behaviors of Random Telegraph Noise (RTN) are proposed. Complex waveforms are clearly visualized using Time Lag Plots. Bias dependence of statistically extracted average trap number is discussed, with emphasis on the importance of undetectable traps on product reliability.

New analysis methods for comprehensive understanding of Random Telegraph Noise

A single-charge-based random fluctuation model suited for analyzing both random telegraph noise (RTN) and intrinsic channel transistors (UTB-SOI, FinFET etc) is proposed Combining a quantitative formula for the worst case V TH shift (ΔV TH ) with measured data of RTN amplitude distributions, it is shown that RTN should not be ignored for scaled SRAM design The model also shows that scaling of intrinsic channel FETs will be limited by the fluctuations caused by residual random charge, which rapidly increase in proportion to 1/LW

Single-charge-based modeling of transistor characteristics fluctuations based on statistical measurement of RTN amplitude

A new accelerated testing scheme for detecting SRAM bit failure caused by random telegraph noise (RTN) is proposed. By repeatedly monitoring the fail bit count (FBC) under a reduced margin operation condition, increasing trend of FBC along time was clearly observed, which is believed to be caused by RTN. In addition, physics-based ultra-fast Monte Carlo RTN simulation program has been developed, which quantitatively reproduces the test results. By using the simulation calibrated by the test, product reliability against RTN can be accurately predicted.

Kiyotaka Imai

Papers

The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling

NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-/spl mu/m gate CMOS generation

New analysis methods for comprehensive understanding of Random Telegraph Noise

Single-charge-based modeling of transistor characteristics fluctuations based on statistical measurement of RTN amplitude

Direct observation of RTN-induced SRAM failure by accelerated testing and its application to product reliability assessment