A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.

System and method for product yield prediction

A method and apparatus for measuring electrical noise in devices is disclosed that comprises two distinct measurement phases. In one phase, the differential output resistance, rab, between a first terminal, a, and a second terminal, b, of the device under test is measured. In the second phase, a voltage, VL (t), is measured across a load resistance, RL, that is in series with the first terminal, a, of the device under test. Then the output voltage noise spectral density, SVL, is determined based on a fourier transform of the voltage, VL (t); and the output current noise spectral density, Sia, is determined based on the output voltage noise spectral density, SVL, the load resistance, RL, and the differential output resistance, rab.

Method and apparatus for measuring electrical noise in devices

A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may be substituted for the diode. The use of the diode as an antifuse is also disclosed.

Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure

Process monitoring circuitry according to the invention incorporates additional routing structures that approximate signal delays due to long metal routing paths. The additional process monitor circuitry builds upon existing approaches without increasing the die size of an integrated circuit through the utilization of excess silicon space available between the bonding pads and the scribe lines of an integrated circuit wafer. More specifically, supplemental metal routing lines and vias are included in the delay paths of process monitor circuitry and located on the integrated circuit such that impact to other metal signal lines/vias used in the actual design is minimized. The supplemental metal routing lines are disposed in unused routable silicon space, such that no silicon area penalty is suffered as a result of having long metal routing lines. During the testing of an integrated circuit incorporating the improved process monitor circuitry, test signals for determining the relative strength of different types of transistors of the integrated circuit are extracted. These test signals are compared to simulated delay values that reflect the delays of the additional metal routing lines and vias. Extreme process variations cause the values provided by the process monitor's circuitry to fall outside the set of permissible values determined through three-dimensional simulation. Thus, process monitoring circuitry according to the present invention improves the fault coverage provided by the testing procedures for an integrated circuit by providing information regarding process variations in different metal layers, and may be utilized as a surrogate for observable path testing.

Process monitor circuitry for integrated circuits

Within both an anti-fuse structure and a method for operating the anti-fuse structure there is employed a semiconductor substrate having a first region adjoining a second region, where there is formed a metal oxide semiconductor field effect transistor within and upon the first region of the semiconductor substrate and a metal oxide semiconductor capacitor within the upon the second region of the semiconductor substrate. Further, within the anti-fuse structure: (1) a gate dielectric layer within the metal oxide semiconductor field effect transistor is thicker than a capacitive dielectric layer within the metal oxide semiconductor capacitor; and (2) the metal oxide semiconductor capacitor is formed employing as a first capacitor plate a doped well within the semiconductor substrate of equivalent polarity with and overlapping with a source/drain region within the metal oxide semiconductor field effect transistor. The anti-fuse structure has a comparatively low programming voltage which does not electrically overstress adjacent microelectronic devices.

Low programming voltage anti-fuse structure

The reliability of thin film insulators is determined with noise measurements which find the barrier height mean and standard deviation A constant voltage source is applied across the thin film insulator A low noise amplifier is connected across a resistor which is in series with the insulator A spectrum analyzer is connected to the low noise amplifier The power density is obtained by observing the output of a spectrum analyzer The current spectral density is compared to a predetermined reference to detect the presence of defects in the insulator

Klaus A. Anselm

Papers

Method for detecting defects in semiconductor insulators