A high breakdown voltage semiconductor device comprising a semiconductor substrate an insulating layer formed on the semiconductor substrate, a high resistance semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction, a first low resistance region of a first conductivity type formed in a central surface portion of the element region, and a second low resistance region of a second conductivity type formed in a peripheral surface portion of the element region. Dose of impurities in the element region is set such that a portion of the element region between the first low resistance region and the second low resistance region is completely depleted when voltage is applied between the first and second low resistance regions.

High-breakdown-voltage semiconductor device

A diode having a p + semiconductor region, an n − drift region and an n + semiconductor region is formed in an SOI layer. An SiC layer is formed in the bottom surface of a semiconductor layer. Further, a capacitive coupled multiple field plate including conductive layers is formed between cathode and anode electrodes. As a result, a semiconductor device with a lateral high breakdown voltage element having extremely high breakdown voltage which is never restricted by electric field concentration in the surface of the SOI layer can be achieved.

Semiconductor device having lateral high breakdown voltage element

A semiconductor device structure in which a power semiconductor device is used as the substrate for the structure. Initially, a first metallization layer is formed on the power semiconductor device. Then, a dielectric passivation layer is formed over the first metallization layer, the dielectric passivation layer having apertures through which the first metallization layer may be accessed. A polymer passivation layer is then formed on the dielectric passivation layer, the polymer passivation layer also having apertures through which the first metallization layer and the dielectric passivation layer may be accessed. A second metallization layer is then formed on the polymer passivation layer and at least one electronic component is attached to the polymer passivation layer or the second metallization layer. The polymer passivation layer provides galvanic isolation between the power semiconductor device and the electronic component.

Isolated multi-chip devices

A composite dieletric film for final passivation of an integrated circuit. First, plasma-enhanced TEOS oxide is deposited to a thickness of 2000 Å, followed by thermal O 3 -TEOS oxide to a thickness of 8000 Å, and then silicon nitride to a thickness of 10,000 Å.

Composite dielectric passivation of high density circuits

The invention discloses a VDMOS transistor and a preparation method thereof and belongs to the field of semiconductors. The VDMOS transistor comprises a first conduction type substrate, a first conduction type epitaxial layer, a second conduction type injection region, a first conduction type highly doped source region and a grid structure, the second conduction type injection region and the first conduction type highly doped source region are arranged in the epitaxial layer, and the grid structure comprises a grid insulating layer, a semi-insulating polycrystalline silicon layer, a silicon oxynitride layer and a polycrystalline silicon layer. The grid insulating layer is arranged above a drift region of the epitaxial layer, the semi-insulating polycrystalline silicon layer is arranged above the grid insulating layer, the silicon oxynitride layer is arranged above a channel region, and the polycrystalline silicon layer is covered on the semi-insulating polycrystalline silicon layer and the silicon oxynitride layer. A heat nitriding silicon oxynitride layer is introduced into the preparation method, a traditional silica layer which is used as a gate medium layer on a channel is replaced, and the semi-insulating polycrystalline silicon layer is added on an oxide layer which is arranged above the drift region of the epitaxial layer. The VDMOS transistor and the preparation method thereof can obviously reduce grid-drain capacitance and achieve overcoming the defects that insulating performance of the grid insulating layer is poor, current leaking of a grid electrode is increased, and degeneration of the VDMOS performance is unreliable.

VDMOS transistor and preparation method thereof

There is disclosed a power transistor comprising a semiconductor substrate having a PN junction exposed on a major surface of the semiconductor substrate, and a semiinsulative polysilicon film formed on the major surface, the polysilicon film covering the PN junction, the polysilicon film containing at least one of carbon, oxygen, and nitrogen, and the polysilicon film having a thickness of about 3000 Å.

Koshino Yutaka Pat Division

Papers

Semiconductor device with a high breakdown voltage