The present invention provides an apparatus for the horizontal stacking of laminations 10 and donuts to form a stator core. A stator generator frame 2 has multiple keybars 6 that run the axial length of the frame. The laminations 10 have grooves 12 there-in that engage the keybars to provide a secure fit of the laminations to the generator frame. By extending two or more of the keybars 6, these extensions 7 may be used as rails on which the laminations may be horizontally inserted into the stator frame.

Horizontal assembly of stator core using keybar extensions

In the present invention, an input terminal of a flip-flop circuit in master slave form which is formed by connecting two inverters in a loop shape is connected to a first terminal via a first switch circuit, an output terminal of the flip-flop circuit is connected to a second terminal via a second switch circuit, a third switch circuit is provided between the path from the first switch circuit to the input terminal and the second terminal, a fourth switch circuit is provided between the path from the output terminal to the second switch circuit and the first terminal, and through turning ON the first and second switch circuits and turning OFF the third and fourth switch circuits the first terminal is rendered operable as an input terminal and the second terminal is rendered operable as an output terminal, and through turning OFF the first and second switch circuits and turning ON the third and fourth switch circuits the second terminal is rendered operable as an input terminal and the first terminal is rendered operable as an output terminal.

Flip-flop circuit, shift register and scan driving circuit for display device

An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (V ddl ) supply and a high voltage island powered by a high voltage (V ddh ) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.

Multiple voltage integrated circuit and design method therefor

A test circuit (200) furnishes a low battery level signal on the basis of a comparison between a first ratio of the battery potential when the battery (206) is unloaded and a second ratio of the loaded battery potential. The battery test circuit includes a potential divider (210), a comparator (250) and a potential sampler including a storage element (240), a controller (260), a control line (266) and a switch (268). The potential divider is coupled to the battery and includes a first tap (226) and a second tap (224). The potential sampler, which includes a storage element (240), is coupled to the first tap through a switch (268) so that a first ratiometric portion of the unloaded battery voltage is stored on the storage element. The comparator has a first input that is coupled to the storage element and a second input that is coupled to the second tap. The comparator compares the first ratiometric portion of the unloaded battery voltage to a second ratiometric portion of the loaded battery voltage and generates an output (234), which designates a battery test result, on the basis of the comparison.

Low battery tester comparing load and no-load battery voltage

Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage is generated in response to the first ramping voltage. The second ramping voltage has a lower ripple than the first ramping voltage. The second ramping voltage is output as a program voltage for programming a non-volatile memory device. A program voltage generating circuit includes a program voltage generating unit configured to generate an initial voltage, a ramping circuit configured to generate a first ramping voltage responsive to the initial voltage, and a voltage controlling unit configured to generate a second ramping voltage having relatively low ripple and to output the first ramping voltage or the second ramping voltage responsive to a voltage level of the first ramping voltage. Semiconductor memory devices including program voltage generating circuits are also disclosed.

Methods and circuits for generating a high voltage and related semiconductor memory devices

A semiconductor integrated circuit device includes a preceding circuit portion, a flip-flop circuit portion receiving complementary output signals of the preceding circuit portion, for latching data in accordance with the complementary output signals of the preceding circuit portion, and a compensation circuit portion receiving complementary output signals of the flip-flop circuit portion and receiving the complementary output signals of the preceding circuit portion without passing through the flip-flop circuit portion, for compensating driving power and decreasing a delay time of a specific phase. Therefore, the delay time of the semiconductor integrated circuit device can be decreased in one phase (specific phase).

Semiconductor integrated circuit device having edge trigger flip-flop circuit for decreasing delay time

A Bi-CMOS logic circuit includes first and second bipolar transistors connected in series between a first power source and a second power source. An output signal is drawn from a connection node at which first and second bipolar transistors are connected in series. The Bi-CMOS logic circuit also includes a first impedance element, connected between a base and an emitter of the first bipolar transistor, providing a first impedance, and a second impedance element, connected between a base of the second bipolar transistor and an emitter thereof, providing a second impedance. Further, the Bi-CMOS logic circuit includes a first MOS transistor connected between the collector of the first bipolar transistor and the base thereof, a second MOS transistor connected between the collector of the second bipolar transistor and the base thereof, an input signal being applied to gates of the first and second MOS transistors; and a third MOS transistor connected between the base of the first bipolar transistor and the second power source. The third MOS transistor has the gate thereof connected to the base of the second bipolar transistor.

Bi-CMOS logic circuit having full voltage swing and rapid turn-off

A Bi-CMOS logic circuit includes a Bi-CMOS circuit which is composed of first and second bipolar transistors (Q1, Q2), first and second resistors (R1, R2) and first and second MOS transistors (MP1, MN1). An input signal (IN) is applied to the gates of the first and second MOS transistors, and an output signal (OUT) is drawn from a connection node where the first and second bipolar transistors are connected in series between first and second power sources. A third MOS transistor (MP2) is connected between the collector and emitter of the first bipolar transistor. The input signal is applied to the gate of the third MOS transistor. In place of or in addition to the third MOS transistor, a fourth MOS transistor (MN2) is provided which is connected between the collector and emitter of the second bipolar transistor. The third and fourth MOS transistors function to decrease roundings of rising and falling edges of the waveform of the output signal.

Bi-cmos logic circuit

A Bi-CMOS circuit includes a first bipolar, a second bipolar transistor and a CMOS control unit for performing switching controls of the first and second bipolar transistors on the basis of an input signal applied to an input terminal and for controlling an output signal output via the output terminal on the basis of the input signal. A turn-OFF unit temporality couples the base of the first bipolar transistor to a low-potential side power supply line on the basis of a current flowing in said control means when the first bipolar transistor is turned OFF, so that the first bipolar transistor can be rapidly turned OFF.

Kou Ebihara

Papers

Semiconductor integrated circuit device having edge trigger flip-flop circuit for decreasing delay time

Bi-CMOS logic circuit having full voltage swing and rapid turn-off

Bi-cmos logic circuit

Bi-CMOS circuits with enhanced power supply noise suppression and enhanced speed