A semiconductor integrated circuit includes first and second data paths, first to third flip flops and logic circuits. The first data path transfers input data. The first flip flop is coupled to the first data path for temporally storing data received from the first data path in response to a first clock signal that is delayed from a reference clock signal. One of the logic circuits receives data from the first flip flop and another logic circuit outputs output data. The second flip flop is connected between the logic circuits for transferring signal between them in response to the reference clock signal. The third flip flop is connected to another logic circuit for outputting the output data in response to a second clock signal that is advanced from the reference clock signal. The second data path transfers data received from the third flip flop.

Semiconductor integrated circuit

A hold time error list, having for each hold time error path a hold time error value satisfying plural timing constraints, and more specifically a maximum hold time error value for each of timing constraints, as well as a setup time margin map allocating to path a setup time margin satisfying plural timing constraints for each setup time error path, and more specifically minimum value of setup time margins for the same path for each timing constraint, are generated. Also, referring to this setup time margin map, delay buffers, which reduces or eliminates hold time error of hold error list, and a delay of which is within the range of delay amounts and positions equal to or lower than the setup time margin, are inserted. Referring to the setup time margin map, it is possible to insert delay buffer to correct hold time error without causing new setup time errors.

Hold time error correction method and correction program for integrated circuits

In the present invention, an input terminal of a flip-flop circuit in master slave form which is formed by connecting two inverters in a loop shape is connected to a first terminal via a first switch circuit, an output terminal of the flip-flop circuit is connected to a second terminal via a second switch circuit, a third switch circuit is provided between the path from the first switch circuit to the input terminal and the second terminal, a fourth switch circuit is provided between the path from the output terminal to the second switch circuit and the first terminal, and through turning ON the first and second switch circuits and turning OFF the third and fourth switch circuits the first terminal is rendered operable as an input terminal and the second terminal is rendered operable as an output terminal, and through turning OFF the first and second switch circuits and turning ON the third and fourth switch circuits the second terminal is rendered operable as an input terminal and the first terminal is rendered operable as an output terminal.

Flip-flop circuit, shift register and scan driving circuit for display device

In an integrated clock gating (ICG) cell a latch is coupled to a NOR gate. The NOR gate receives an enable signal. The latch is configured to generate a latch output in response to the state of the enable signal. The latch includes a tri-state inverter. A NAND gate is coupled to the latch and the NAND gate is configured to generate an inverted clock signal in response to the latch output and a clock input.

Low clock-power integrated clock gating cell

Flip-flops include a master stage and a slave stage. The master stage is responsive to a first clock signal and has a first pair of differential inputs and a first pair of differential outputs. The slave stage is responsive to a second clock signal and has a second pair of differential inputs coupled to the first pair of differential outputs and a second pair of differential outputs from which true and complementary outputs (Q, QB) of the flip-flop are derived. If the flip-flop is a D-type flip-flop, the first pair of differential inputs receive true and complementary data signals (DATA, DATAB). If the flip-flop is a set-reset (S-R) flip-flop, the first pair of differential inputs receive set and reset signals (SET, RESET).

Integrated circuit flip-flops that utilize master and slave latched sense amplifiers

A semiconductor integrated circuit device includes a preceding circuit portion, a flip-flop circuit portion receiving complementary output signals of the preceding circuit portion, for latching data in accordance with the complementary output signals of the preceding circuit portion, and a compensation circuit portion receiving complementary output signals of the flip-flop circuit portion and receiving the complementary output signals of the preceding circuit portion without passing through the flip-flop circuit portion, for compensating driving power and decreasing a delay time of a specific phase. Therefore, the delay time of the semiconductor integrated circuit device can be decreased in one phase (specific phase).

Semiconductor integrated circuit device having edge trigger flip-flop circuit for decreasing delay time

Input/output AC characteristics of a hard macro cell is specified in advance, delay cells 15 and 16 are provided in the input and output sides of the hard macro cell, and signal propagation delay times of the delay cells 15 and 16 are set so as to satisfy the specifications. These delay times are determined in such a way that no timing error occurs at the data inputs D of the D flip-flops 11 and 22 on condition that D flip-flops 20 and 22 are arranged outside the hard macro cell 10A, the data output end Q of the D flip-flop 20 is directly connected by a line to the data input end DI of the hard macro cell 10A, the data input end of the external synchronous flip-flop 22 is directly connected to the data output end DO of the hard macro cell 10A, and a clock CLK is commonly provided to the clock input ends CK of the hard macro cell 10A and the D flip-flops 20 and 22.

Methods of making hard macro cell using timing interval

PROBLEM TO BE SOLVED: To more simplify a design which uses a hard macro. SOLUTION: The input/output AC characteristics of the hard macro are previously specified, delay cells 15 and 16 are respectively provided on the input side and output side in the hard macro, and the signal propagation delay time of delay cells 15 and 16 is determined so as to satisfy this specification. This specification is made to satisfy such condition not to generate any timing error at D flip-flops 11 and 22 at the time of commonly supplying a clock CLK to the D flip-flops 20 and 22 and a clock input terminal CK of a hard macro 10A by arranging the D flip-flops 20 and 22 outside the hard macro 10A, directly connecting a data output terminal Q of the D flip-flop 20 to a data input terminal DI of the hard macro 10A and directly connecting a data input terminal D of the D flip-flop 22 to a data output terminal DO of the hard macro 10A.

Kunihiko Kawaguchi

Papers

Semiconductor integrated circuit device having edge trigger flip-flop circuit for decreasing delay time

Methods of making hard macro cell using timing interval

Hard macro preparing method, semiconductor chip designing method, and recording medium