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Kozo Harada

Researcher at Mitsubishi Electric

Publications -  11
Citations -  83

Kozo Harada is an academic researcher from Mitsubishi Electric. The author has contributed to research in topics: Semiconductor device & Flip chip. The author has an hindex of 3, co-authored 11 publications receiving 76 citations.

Papers
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Journal ArticleDOI

Study of package warp behavior for high-performance flip-chip BGA

TL;DR: An optimized underfill resin is proposed that can achieve low package warpage and a long fatigue life of the solder bump and the future trends in under Fill resin will be to have properties of extremely low elastic modulus and non-linear properties such as creep.
Proceedings ArticleDOI

Analysis of solder joint fracture under mechanical bending test

Abstract: 1. Abstract Recently, Electroless-Nickel and Immersion Gold (ENIG) plating has been applied for metalization of package substrate, because of the difficulties of routing for high pin count package. And we have been experienced that ENIG may cause the electrical open failure by some mechanical stress at In-Circuit Test (ICT) after package mount on printed circuit board (PCB), for example. In order to clarify the phenomena of solder joint fracture which causes open failure, we have been performing a four-point bending test and succeeded to optimize the condition of four-point bending test getting same phenomena as actual failure mode. This test procedure will be effective to simulate the reliability of solder joint. For fourpoint bending test, the daisy chained PCB and Flip-Chip BGA (FC-BGA) package which is 1848pin with 45mm body size, l.0mm ball pitch, were used.
Proceedings ArticleDOI

Thermo-electromigration phenomenon of solder bump, leading to flip-chip devices with 5,000 bumps

TL;DR: In this paper, the lifetime of a Flip-chip BGA (FC-BGA) package applied to a high-density organic substrate has been investigated, and the lifetime was predicted more than 20 years with the current being 160 mA/bump in 220 /spl mu/m pitch cases.
Patent

Semiconductor device and electric power converter

TL;DR: A semiconductor device is characterized by comprising: an insulating substrate 52 which has conductor layers 51, 53 on the upper surface and the lower surface, respectively, while having a semiconductor element 4 mounted on the conductor layer 51 on upper surface; a base plate 1 which is joined to the conductor layers 53 on lower surface; and a case member 2 which surrounds the substrate 52 and is bonded to a surface of the base plate as discussed by the authors.
Patent

Semiconductor device and method for manufacturing same

Abstract: A semiconductor device includes: an insulating substrate having an upper surface on which a semiconductor element is mounted; a base plate joined to a lower surface of the insulating substrate; a case member that surrounds the insulating substrate and that is in contact with a surface of the base plate to which the insulating substrate is joined; a sealing resin provided in a region surrounded by the base plate and the case member; a cover member facing a surface of the sealing resin and fixed to the case member; and a holding plate, a lower surface of the holding plate and a portion of a side surface of the holding plate being in close contact with the surface of the sealing resin, an upper surface of the holding plate being fixed to and protruding from a surface of the cover member facing the surface of the sealing resin.