An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Silicides and ohmic contacts

An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

A plurality of standard cells 10 are arranged to form a channel-less standard cell array 1 , which has vertical and horizontal sides. A plurality of first proximity dummy cells 20 are arranged along each of the vertical sides of the standard cell array to form a first proximity dummy bands 20 such that the upper and lower sides of the first proximity dummy cells are in contact with each other and such that the left or right side of each of the first proximity dummy cells is in contact with the vertical side of the standard cell array 1 . Furthermore, a plurality of second proximity dummy bands are arranged along each of the horizontal sides of the standard cell array to form a second proximity dummy bands such that the upper or lower side of each of the second proximity dummy cells is in contact with the horizontal side of the standard cell 1.

Layout method of semiconductor integrated circuit, layout structure thereof, and photomask for forming the layout structure

The manufacturing method uses a substrate body comprising a semiconductor substrate having a cell region (1) for forming a memory cell portion and a circuit region (2) for forming a peripheral circuit portion, in which a diffusion layer is formed to the semiconductor substrate in the circuit region (2) and a first interlayer insulation film is formed on the semiconductor substrate, and comprises conducting a step of forming a peripheral circuit including a step of forming a connection hole through a first interlayer insulation film in the circuit region (2) so as to expose the diffusion layer at the bottom, a step of ion implanting impurities to the diffusion layer in the vicinity of the bottom of the connection hole and a step of conducting a heat treatment for activating the impurities introduced into the diffusion layer. Subsequently, a cell region processing step having a step of forming a capacitor on the substrate body in the cell region (1) is conducted. A highly dielectric material is used for the material of the dielectric film of the capacitor, so that the capacity of the capacitor is not lowered even if the compensating diffusion layer is formed in the step of forming the peripheral circuit.

Method of manufacturing a semiconductor device

PURPOSE: To suppress noise and surge voltages by detecting a voltage between first and second terminals, changing the resistance value of a resistor corresponding to this detected Value and decelerating speed to increase or decrease a gate voltage. CONSTITUTION: When an input signal Soff is supplied from a control circuit 1 to an SW1, the SW1 is turned on, an electric charge charged through a first resisting means 3 to a gate capacitor Cge of a Q1 is discharged, and the Q1 is turned off. When an input signal Son is supplied from the circuit 1 to an SW2, the SW2 is turned on, the electric charge is charged from a control power source Vcc through a second resisting means 4 to the gate capacitor Cge, and the Q1 is turned off. In this case, the resistance value is changed by the means 3 and 4 respectively corresponding to the output of a voltage detecting means 5 to detect the collector voltage of the Q1. Namely, when a collector voltage is less than a prescribed value, the resistance value of the means 3 and 4 is changed into low resistance and when the collector voltage is larger than the prescribed value, the resistance value is changed into high resistance. At the time of turn-off, the collector voltage is increased, the means 3 is changed into the high resistance, and discharging from the capacitor Cge is delayed. COPYRIGHT: (C)1994,JPO

Method and circuit for driving voltage driven element

It is an object of the present invention to provide a technology of a semiconductor integrated circuitry that allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operated faster In a method for manufacturing such a semiconductor integrated circuitry of the present invention, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1 , and on side surfaces of each of the gate electrodes is formed the first side wall spacer 14 composed of silicon nitride and the second side wall spacer 15 composed of silicon oxide Then, in the selecting MISFET Qs in the DRAM memory cell area are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and are formed connecting portion connecting a conductor 20 to a bit line BL In addition, in the N channel MISFETs Qn 1 and Qn 2 , and in the P channel MISFET Qp 1 in areas other than the DRAM memory cell area are formed high density N-type semiconductor areas 16 and 16 b , as well as a high density P-type semiconductor area 17 in a self-matching manner with respect to the second side wall spacers 15

Semiconductor integrated circuit device and method for manufacturing the same

A semiconductor device includes grooves defining an active region, including a MISFET, and dummy regions A first interlayer insulation film is formed over the MISFET, the active region and the dummy regions A first wiring, and first and second dummy wirings are formed over the first interlayer insulation film A second interlayer insulation film is formed over the first wiring and the dummy wirings The second dummy wirings are arranged between the first wiring and the first dummy wirings, and the pitch of the first dummy wirings is larger than that of the second dummy wirings In planar view, the first and second dummy wirings are arranged over the dummy regions, and the size of each of the first dummy wirings is larger than size of each of the second dummy wirings The first wiring and the first and second dummy wirings are formed of copper as a major component

Semiconductor device and a method of manufacturing the same and designing the same

In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.

Method of making a semiconductor memory circuit device

A method for fabricating a semiconductor integrated circuit device including a memory cell of a MISFET and a capacitor element formed in a memory cell-forming region of a semiconductor substrate, and an n channel-type MISFET and a p channel-type MISFET in a peripheral circuit-forming region, including: forming a gate insulating film on a semiconductor substrate; forming a polysilicon film and a high melting metal film on the gate insulating film, patterning to form a gate electrode in a memory cell-forming region and in a peripheral circuit-forming region, respectively; removing the high melting metal film from the gate electrode of the peripheral circuit-forming region; and depositing a metal layer over the peripheral circuit-forming region, followed by thermal treatment to form a silicide film on the polysilicon film in the gate electrode and a high concentration diffusion layer of the peripheral circuit-forming region.

Kozo Watanabe

Papers

Method and circuit for driving voltage driven element

Semiconductor integrated circuit device and method for manufacturing the same

Semiconductor device and a method of manufacturing the same and designing the same

Method of making a semiconductor memory circuit device

Method for fabricating a semiconductor integrated circuit device