This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved.

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Computer-aided design of analog and mixed-signal integrated circuits

A simple optimization procedure for constraint-based problems is described which works with a simplified cost function or even without one. The simplification of the problem formulation makes this method particularly attractive. The new method lends itself to parallel computation and is well suited for constraint satisfaction, constrained optimization, and design centering problems. A further asset is its self-steering property which makes the new method easy to use.

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System design by constraint adaptation and differential evolution

An automatic test pattern generation system, SOCRATES, is presented. SOCRATES includes several novel concepts and techniques that significantly improve and accelerate the automatic test pattern generation process for combinational and scan-based circuits. Based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures are described. The application of these techniques leads to a considerable reduction of the number of backtrackings and an earlier recognition of conflicts and redundancies. Several experiments using a set of combinational benchmark circuits demonstrate the efficiency of SOCRATES and its cost-effectiveness, even in a workstation environment. >

Socrates : A Highly Efficient Automatic Test Pattern Generation System

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

SOCRATES: a highly efficient automatic test pattern generation system

In this paper, a new methodology for integrated circuit design considering the inevitable manufacturing and operating tolerances is presented. It is based on a new concept for specification analysis that provides exact worst-case transistor model parameters and exact worst-case operating conditions. Corresponding worst-case distances provide a key measure for the performance, the yield, and the robustness of a circuit. A new deterministic method for parametric circuit design that is based on worst-case distances is presented. It comprises nominal design, worst-case analysis, yield optimization, and design centering. In contrast to current approaches, it uses standard circuit simulators and at the same time considers deterministic design parameters of integrated circuits at reasonable computational costs. The most serious disadvantage of geometric approaches to design centering is eliminated, as the method's complexity increases only linearly with the number of design variables. >

Circuit analysis and optimization driven by worst-case distances

This paper presents the sizing rules method for analog CMOS circuit design that consists of: first, the development of a hierarchical library of transistor pair groups as basic building blocks for analog CMOS circuits; second, the derivation of a hierarchical generic list of constraints that must be satisfied to guarantee the function of each block and its reliability with respect to physical effects; and third, the development of an automatic recognition of building blocks in a circuit schematic. The sizing rules method efficiently captures design knowledge on the technology-specific level of transistor pair groups. This reduces the preparatory modeling effort for analog circuit synthesis. Results of industrial applications to circuit sizing, design centering, response surface modeling and analog placement show the significance of the sizing rules method. Sizing rules especially make sure that automatic circuit sizing and design centering lead to technically meaningful and robust results.

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The sizing rules method for analog integrated circuit design

The principles of fault simulation and fault grading are introduced by a general description of the problem. Based upon the well-known concept of restricting fault simulation to the fanout stems and of combining it with a backward traversal inside the fanout-free regions of the circuit, proposals are presented to further accelerate fault simulation and fault grading. These proposals aim at parallel processing of patterns at all stages of the calculation procedure, at reducing the number of fanout stems for which a fault simulation has to be carried out, and at taking advantage of structural characteristics of the circuit. An experiment with a set of benchmark circuits demonstrates the efficiency of the proposed approaches.

Accelerated Fault Simulation and Fault Grading in Combinational Circuits

This paper presents a method to consider local process variations, which crucially influence the mismatch-sensitive analog components, within a new simulation-based analog synthesis tool called WiCkeD. WiCkeD includes tolerance analysis, performance optimization and design centering, and is a university tool used in industry for the design of analog CMOS circuits.

WiCkeD: analog circuit synthesis incorporating mismatch

We present a new method for mismatch analysis and automatic yield optimization of analog integrated circuits with respect to global, local and operational tolerances Effectiveness and efficiency of yield estimation and optimization are guaranteed by consideration of feasibility regions and by performance linearization at worst-case points The proposed methods were successfully applied to two example circuits for an industrial fabrication process

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Kurt Antreich

Papers

Circuit analysis and optimization driven by worst-case distances

The sizing rules method for analog integrated circuit design

Accelerated Fault Simulation and Fault Grading in Combinational Circuits

WiCkeD: analog circuit synthesis incorporating mismatch

Mismatch analysis and direct yield optimization by spec-wise linearization and feasibility-guided search