The conventional n-channel silicon-gate MOS technology faces limitations due to poly-sheet resistance, patterning, and overall process compatibility as feature dimensions shrink and circuit sizes increase. This work describes an investigation of refractory metals as alternate gate material due to their potential advantages in terms of patternability, film sheet resistance that is 50 to 100 times lower comparable to polysilicon, and circuit layout options with improved performance and cost effectiveness. A process was developed for fabrication of NMOS devices using electron-beam direct writing, refractory metal gates and interconnects. Evaporated as well as sputtered molybdenum and tungsten show columnar crystalline structure allowing reproducible patterning of 1-µm lines with the conventional plasma etch techniques. Sheet resistivities of 0.25 Ω/□ and 0.4 Ω/□ were achieved for 3500-A Mo and W films, respectively. Basic parameters such as electronic work function, interface, and surface state charge densities and MOS transistor threshold voltages were determined from metal gate devices with 200-800-A oxides. Flat-band voltages of -0.2 V with mid 1010cm-2interface charges were achieved. Mo-Al-Si double-level metal structure with contacts as small as 2 µm2were fabricated. Considerable improvement in the speed of the LSI circuits fabricated with these high-conductivity gates was demonstrated through computer simulation. Improved circuit layouts of static and dynamic memory cells for speed, power, and density optimization can be achieved. A four-mask process with the simplicity of aluminum gate technology and the performance of current n-channel silicon gate MOS process is proposed.

Refractory metal gate processes for VLSI applications

A new technology based on the anisotropic etching of silicon is presented for the reahzation of complementary devices. Anisotropic etching is performed on (100) oriented slices, where large areas, corresponding to complete devices, are etched down to a depth of a few microns. The etching process is discussed and optimized. This basic structure is applied to two new methods for developing silicon- gate complementary MOS (C-MOS) transistors. High-voltage, p-channel, MOS transistors compatible with the low-voltage, high-density, C-MOS are also prbsented. The advantages of the technology are discussed.

A new C-MOS technology using anisotropic etching of silicon

Lasers offer a diverse approach to fabricating oxide films for a wide variety of applications. This paper will review the field of laser oxidation in general but particular attention will be focused on oxide formation on silicon. Two main areas will be detailed, namely Laser Chemical Vapor Deposition (LCVD) and Laser Pyrolytic Growth (LPG). The kinetics involved with film preparation will be discussed while the various structural, optical and electrical properties of the films will be compared.

Laser assisted pyrolytic growth and photochemical deposition of thin oxide films.

Modulation of the conductance of a thin layer by surface charges, a concept that goes back to 1930, was revived for semiconductors in 1948.233 Practical devices did not ensue until about 1960, when diffusion and oxide technologies for Si were developed. MOSFET structures manufactured during the next few years are illustrated in Fig. 7.1. The current flows by majority carrier movement from the source to drain and is controlled by the voltage on the insulated metal gate which determines the channel charge. In the n-channel enhancement type structure [see Fig. 7.1(a)] the channel is not initially present and must be induced by a positive gate voltage V GS . A threshold voltage V T is needed before any usable characteristic is obtained. In the n-channel depletion type structure [see Fig. 7.1(b)] the channel is already present (as a result of a shallow n-type diffusion or implant or as a result of interface conditions). This channel can be partially depleted by a negative gate voltage or enhanced by a positive gate voltage.

Insulated Gate Field-Effect-Transistors: MOSFETs, IGFETs and Related Devices

63 1 Abstract-The conventional n-channel silicon-gate MOS technology faces limitations due to poly-sheet resistance, patterning, and overall process compatibility as feature dimensions shrink and circuit sizes in- crease. This work describes an investigation of refractory metals as alternate gate material due to their potential advantages in terms of patternability, film sheet resistance that is 50 to 100 times lower com- parable to polysilicon, and circuit layout options with improved perfor- mance and cost effectiveness. A process was developed for fabrication of NMOS devices using electron-beam direct writing, refractory metal gates and interconnects. Evaporated as well as sputtered molybdenum and tungsten show columnar crystalline structure allowing reproducible patterning of 1-pm lines with the conventional plasma etch techniques. Sheet resistivities of 0.25 sl/O and 0.4 fZ/O were achieved for 3500-8 Mo and W films, respectively. Basic parameters such as electronic work function, interface, and surface state charge densities and MOS transis- tor threshold voltages were determined from metal gate devices with 200-800-8 oxides. Flat-band voltages of -0.2 V with mid 1O1O cm-2 interface charges were achieved. Mo-Al-Si double-level metal structure with contacts as small as 2 pm2 were fabricated. Considerable improvement in the speed of the LSI circuits fabricated with these high-conductivity gates was demonstrated through computer simulation. Improved circuit layouts of static and dynamic memory cells for speed, power, and density optimization can be achieved. A four-mask process with the simplicity of aluminum gate technology and the performance of current n-channel silicon gate MOS process is proposed.

Refractory Metal Gate Processes for

This paper describes an extension of the well-known self-registered gate PMOS technology for fabricating complementary MOS (CMOS) transistors. Exclusive usage of doped silane oxides as diffusion sources provides accurate and repeatable control of the n-channel-threshold voltage. The use of doped-oxide diffusion sources also makes possible a novel diffusion technique where the n- and p-channel source and drain diffusions can be performed simultaneously with independent control of sheet resistivity. This technique eliminates one high-temperature operation; at the same time, the doped-oxide diffusion sources can be deposited in such a manner as to allow their differing etch rates to provide favorable slopes on the edges of contact windows, a feature that increases yield and reliability. A description of the process is provided along with an electrical characterization of the devices fabricated using this process.

L.H. Hall

Papers

The extension of self-registered gate and doped-oxide diffusion technology to the fabrication of complementary MOS transistors