International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Preface. 1 Introduction and survey. 1.1 Information, computers and quantum mechanics. 1.1.1 Digital information. 1.1.2 Moore's law. 1.1.3 Emergence of quantum behavior. 1.1.4 Energy dissipation in computers. 1.2 Quantum computer basics. 1.2.1 Quantum information. 1.2.2 Quantum communication. 1.2.3 Basics of quantum information processing. 1.2.4 Decoherence. 1.2.5 Implementation. 1.3 History of quantum information processing. 1.3.1 Initial ideas. 1.3.2 Quantum algorithms. 1.3.3 Implementations. 2 Physics of computation. 2.1 Physical laws and information processing. 2.1.1 Hardware representation. 2.1.2 Quantum vs. classical information processing. 2.2 Limitations on computer performance. 2.2.1 Switching energy. 2.2.2 Entropy generation and Maxwell's demon. 2.2.3 Reversible logic. 2.2.4 Reversible gates for universal computers. 2.2.5 Processing speed. 2.2.6 Storage density. 2.3 The ultimate laptop. 2.3.1 Processing speed. 2.3.2 Maximum storage density. 3 Elements of classical computer science. 3.1 Bits of history. 3.2 Boolean algebra and logic gates. 3.2.1 Bits and gates. 3.2.2 2 bit logic gates. 3.2.3 Minimum set of irreversible gates. 3.2.4 Minimum set of reversible gates. 3.2.5 The CNOT gate. 3.2.6 The Toffoli gate. 3.2.7 The Fredkin gate. 3.3 Universal computers. 3.3.1 The Turing machine. 3.3.2 The Church Turing hypothesis. 3.4 Complexity and algorithms. 3.4.1 Complexity classes. 3.4.2 Hard and impossible problems. 4 Quantum mechanics. 4.1 General structure. 4.1.1 Spectral lines and stationary states. 4.1.2 Vectors in Hilbert space. 4.1.3 Operators in Hilbert space. 4.1.4 Dynamics and the Hamiltonian operator. 4.1.5 Measurements. 4.2 Quantum states. 4.2.1 The two dimensional Hilbert space: qubits, spins, and photons. 4.2.2 Hamiltonian and evolution. 4.2.3 Two or more qubits. 4.2.4 Density operator. 4.2.5 Entanglement and mixing. 4.2.6 Quantification of entanglement. 4.2.7 Bloch sphere. 4.2.8 EPR correlations. 4.2.9 Bell's theorem. 4.2.10 Violation of Bell's inequality. 4.2.11 The no cloning theorem. 4.3 Measurement revisited. 4.3.1 Quantum mechanical projection postulate. 4.3.2 The Copenhagen interpretation. 4.3.3 Von Neumann's model. 5 Quantum bits and quantum gates. 5.1 Single qubit gates. 5.1.1 Introduction. 5.1.2 Rotations around coordinate axes. 5.1.3 General rotations. 5.1.4 Composite rotations. 5.2 Two qubit gates. 5.2.1 Controlled gates. 5.2.2 Composite gates. 5.3 Universal sets of gates. 5.3.1 Choice of set. 5.3.2 Unitary operations. 5.3.3 Two qubit operations. 5.3.4 Approximating single qubit gates. 6 Feynman's contribution. 6.1 Simulating physics with computers. 6.1.1 Discrete system representations. 6.1.2 Probabilistic simulations. 6.2 Quantum mechanical computers. 6.2.1 Simple gates. 6.2.2 Adder circuits. 6.2.3 Qubit raising and lowering operators. 6.2.4 Adder Hamiltonian. 7 Errors and decoherence. 7.1 Motivation. 7.1.1 Sources of error. 7.1.2 A counterstrategy. 7.2 Decoherence. 7.2.1 Phenomenology. 7.2.2 Semiclassical description. 7.2.3 Quantum mechanical model. 7.2.4 Entanglement and mixing. 7.3 Error correction. 7.3.1 Basics. 7.3.2 Classical error correction. 7.3.3 Quantum error correction. 7.3.4 Single spin flip error. 7.3.5 Continuous phase errors. 7.3.6 General single qubit errors. 7.3.7 The quantum Zeno effect. 7.3.8 Stabilizer codes. 7.3.9 Fault tolerant computing. 7.4 Avoiding errors. 7.4.1 Basics. 7.4.2 Decoherence free subspaces. 7.4.3 NMR in Liquids. 7.4.4 Scaling considerations. 8 Tasks for quantum computers. 8.1 Quantum versus classical algorithms. 8.1.1 Why Quantum? 8.1.2 Classes of quantum algorithms. 8.2 The Deutsch algorithm: Looking at both sides of a coin at the same time. 8.2.1 Functions and their properties. 8.2.2 Example: one qubit functions. 8.2.3 Evaluation. 8.2.4 Many qubits. 8.2.5 Extensions and generalizations. 8.3 The Shor algorithm: It's prime time. 8.3.1 Some number theory. 8.3.2 Factoring strategy. 8.3.3 The core of Shor's algorithm. 8.3.4 The quantum Fourier transform. 8.3.5 Gates for the QFT. 8.4 The Grover algorithm: Looking for a needle in a haystack. 8.4.1 Oracle functions. 8.4.2 The search algorithm. 8.4.3 Geometrical analysis. 8.4.4 Quantum counting. 8.4.5 Phase estimation. 8.5 Quantum simulations. 8.5.1 Potential and limitations. 8.5.2 Motivation. 8.5.3 Simulated evolution. 8.5.4 Implementations. 9 How to build a quantum computer. 9.1 Components. 9.1.1 The network model. 9.1.2 Some existing and proposed implementations. 9.2 Requirements for quantum information processing hardware. 9.2.1 Qubits. 9.2.2 Initialization. 9.2.3 Decoherence time. 9.2.4 Quantum gates. 9.2.5 Readout. 9.3 Converting quantum to classical information. 9.3.1 Principle and strategies. 9.3.2 Example: Deutsch Jozsa algorithm. 9.3.3 Effect of correlations. 9.3.4 Repeated measurements. 9.4 Alternatives to the network model. 9.4.1 Linear optics and measurements. 9.4.2 Quantum cellular automata. 9.4.3 One way quantum computer. 10 Liquid state NMR quantum computer. 10.1 Basics of NMR. 10.1.1 System and interactions. 10.1.2 Radio frequency field. 10.1.3 Rotating frame. 10.1.4 Equation of motion. 10.1.5 Evolution. 10.1.6 NMR signals. 10.1.7 Refocusing. 10.2 NMR as a molecular quantum computer. 10.2.1 Spins as qubits. 10.2.2 Coupled spin systems. 10.2.3 Pseudo / effective pure states. 10.2.4 Single qubit gates. 10.2.5 Two qubit gates. 10.2.6 Readout. 10.2.7 Readout in multi spin systems. 10.2.8 Quantum state tomography. 10.2.9 DiVincenzo's criteria. 10.3 NMR Implementation of Shor's algorithm. 10.3.1 Qubit implementation. 10.3.2 Initialization. 10.3.3 Computation. 10.3.4 Readout. 10.3.5 Decoherence. 11 Ion trap quantum computers. 11.1 Trapping ions. 11.1.1 Ions, traps and light. 11.1.2 Linear traps. 11.2 Interaction with light. 11.2.1 Optical transitions. 11.2.2 Motional effects. 11.2.3 Basics of laser cooling. 11.3 Quantum information processing with trapped ions. 11.3.1 Qubits. 11.3.2 Single qubit gates. 11.3.3 Two qubit gates. 11.3.4 Readout. 11.4 Experimental implementations. 11.4.1 Systems. 11.4.2 Some results. 11.4.3 Problems. 12 Solid state quantum computers. 12.1 Solid state NMR/EPR. 12.1.1 Scaling behavior of NMR quantum information processors. 12.1.2 31P in silicon. 12.1.3 Other proposals. 12.1.4 Single spin readout. 12.2 Superconducting systems. 12.2.1 Charge qubits. 12.2.2 Flux qubits. 12.2.3 Gate operations. 12.2.4 Readout. 12.3 Semiconductor qubits. 12.3.1 Materials. 12.3.2 Excitons in quantum dots. 12.3.3 Electron spin qubits. 13 Quantum communication. 13.1 Quantum only tasks. 13.1.1 Quantum teleportation. 13.1.2 (Super ) Dense coding. 13.1.3 Quantum key distribution. 13.2 Information theory. 13.2.1 A few bits of classical information theory. 13.2.2 A few bits of quantum information theory. Appendix. A. Two spins 1/2: Singlet and triplet states. B. Symbols and abbreviations. Bibliography. Index.

Quantum Computing: A Short Course from Theory to Experiment

Real-time video processing has found its range of applications from defense to consumer electronics for surveillance, video conferencing, etc. With the advent of Field Programmable Gate Arrays (FPGAs), flexible real-time video processing systems which can meet hard real-time constraints are easily realized with short development time. Most of the existing solutions have high utilization of system resources and are not quite flexible with many applications. Here we propose a hardware–software co-design for an FPGA-based real-time video processing system to convert video in standard Phase Alternating Line (PAL) 576i format to standard video of Video Graphics Array (VGA)/Super Video Graphics Array (SVGA) format with little utilization of resources. Switching between multiple video streams, character/text overlaying, and skin color detection are also incorporated with the system. The system is also adaptable for rugged applications. VHSIC Hardware Description Language (VHDL) codes for the architecture were synthesized using Altera Quartus II and targeted for Altera Stratix I FPGA. Results achieved confirm that the proposed system performs efficient conversion with very less resource utilization compared to the existing solutions. Since the proposed system is also flexible, many other applications can be incorporated in the future.

An efficient and adaptable multimedia system for converting PAL to VGA in real-time video processing

This paper suggests an optimisation approach in heterogeneous computing systems to balance energy power consumption and efficiency. The work proposes a power measurement utility for a reinforcement learning (PMU-RL) algorithm to dynamically adjust the resource utilisation of heterogeneous platforms in order to minimise power consumption. A reinforcement learning (RL) technique is applied to analyse and optimise the resource utilisation of field programmable gate array (FPGA) control state capabilities, which is built for a simulation environment with a Xilinx ZYNQ multi-processor systems-on-chip (MPSoC) board. In this study, the balance operation mode for improving power consumption and performance is established to dynamically change the programmable logic (PL) end work state. It is based on an RL algorithm that can quickly discover the optimization effect of PL on different workloads to improve energy efficiency. The results demonstrate a substantial reduction of 18% in energy consumption without affecting the application’s performance. Thus, the proposed PMU-RL technique has the potential to be considered for other heterogeneous computing platforms.

Energy and performance trade-off optimization in heterogeneous computing via reinforcement learning

The very-large-scale-integration industry has been highly trying to attain miniaturization. This function causes several challenges regarding size, switching speed, power, and fault-tolerant at the...

A Fault-Tolerance Nanoscale Design for Binary-to-Gray Converter based on QCA

Reversible logic computation is one of the most essential promising technologies in designing low-power digital circuits, optical information processing, quantum dot cellular automata, fault tolerant system and nanotechnology. In fact, the conventional digital circuits dissipate a significant amount of energy because several bits of information are deleted during the treatments. In reversible computation, the information bits are not lost. This study presents a novel design of reversible RGB to HMMD converter circuit. The proposed hardware converter is based on several reversible sub-modules as: adder, subtractor, multiplier, register, multiplexer comparator and others. In order to demonstrate the efficiency of the proposed logic design, each sub-module is shown in terms of number of quantum cost needed, gates required delay and garbage outputs produced. Since the works in the field of reversible logic video treatment has only started to bloom, the proposed contribution will engender a new thread of research in the field of reversible real time video treatment.

Design of hardware RGB to HMMD converter based on reversible logic

Quantum dot cellular automata (QCA) is a hopeful technology in the field of nanotechnology that seems to suite well with signal-processing needs. It is concerned with great interest because of its benefits such as ultra-low power consumption, small size and can operate at one Terahertz. The multiply accumulator (MAC) unit is considered as one of the essential operations in digital signal processing (DSP). In the real-time DSP systems, several applications like speech processing, video coding, and digital filtering etc. require MAC operations. However, the power dissipation and area are the most significant aspects in these systems. Here, the authors design low power MAC unit based on QCA technology. QCADesigner version 2.0.3 is used to validate the accuracy of the proposed circuit. The reliability of this unit is taken at different temperatures. The power dissipation is estimated using QCAPro tool. The total power consumed by this unit is 2.183 μW. The proposed circuit has 90% improvement in terms of power over complementary metal–oxide–semiconductor (CMOS) circuits. Since the works in the field of QCA logic signal processing has started to progress, the suggested contribution will give rise to a new thread of research in the field of real-time signal and image treatment.

Design of efficient quantum Dot cellular automata (QCA) multiply accumulate (MAC) unit with power dissipation analysis

The continuous market demands for high performance and energy-efficient computing systems have steered the computational paradigm and technologies towards nanoscale quantum-dot cellular automata (Q...

/pdf/an-efficient-design-of-qca-full-adder-subtractor-with-low-3ziril28di.pdf

An Efficient Design of QCA Full-Adder-Subtractor with Low Power Dissipation

Optimization for power is one of the most important design objectives in modern digital signal processing (DSP) applications. The digital finite duration impulse response (FIR) filter is considered to be one of the most essential components of DSP, and consequently a number of extensive works had been carried out by researchers on the power optimization of the filters. Data-driven clock gating (DDCG) and multibit flip-flops (MBFFs) are two low-power design methods that are used and often treated separately. The combination of these methods into a single algorithm enables further power saving of the FIR filter. The experimental results show that the proposed FIR filter achieves 25% and 22% power consumption reduction compared to that using the conventional design.

/pdf/design-of-low-power-structural-fir-filter-using-data-driven-2okupggkdu.pdf

Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-Flops

In this paper, we focused on
 the study of the MPEG-7 color structure descriptor (CSD) for real-time temporal video segmentation. A new hardware architecture of the CSD was proposed. In the aim of optimizing this implementation in terms of hardware resources and execution time, different algorithm transformations have been tested for the considered application. The CSD was applied for different quantization levels in the HMMD color space and for different grey levels, with and without a frame skip. We have demonstrated that the use of a low number of quantization levels and a frame skip can significantly reduce the complexity and assure a better computing performance while preserving a satisfactory level of accuracy in terms of shot boundary detection rate. This is useful for implementation on resource-constrained hardware platform and multiprocessing applications. The performances of the proposed architecture were evaluated for different quantization levels to show the effect on occupied hardware resources and execution time. The comparative study demonstrates the effectiveness of the proposed architecture, which can operate in real-time video and without restriction on image size. In this work we have also designed a system on chip (SOC) for real-time video summarization based on the CSD. The proposed SOC integrating the CSD module was developed using a platform based on a Xilinx Virtex5 FPGA. A complete demonstration, including CSD extraction, shot boundary detection and key-frames visualization, was realized.

Lamjed Touil

Papers

Design of hardware RGB to HMMD converter based on reversible logic

Design of efficient quantum Dot cellular automata (QCA) multiply accumulate (MAC) unit with power dissipation analysis

An Efficient Design of QCA Full-Adder-Subtractor with Low Power Dissipation

Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-Flops

Adequation and hardware implementation of the color structure descriptor for real-time temporal video segmentation