A system for providing video-on-demand service, broadband internet access and other broadband services over T-carrier systems including a pull multiplexer cherrypicker at the head end is disclosed. The pull multiplexer receives upstream requests and cull out MPEG or other compressed video packets, IP packets and other data packet types to satisfy the requests or to send pushed programming downstream. The downstream can be DSL or HFC. Each customer has a cable modem, DSL modem or a gateway which interfaces multiple signal sources to a LAN to which settop decoders, digital phones, personal computers, digital FAX machines, video cameras, digital VCRs etc. can be attached. Each gateway can coupled the LAN to a DSL line or HFC through a cable modem or a satellite dish through a satellite transceiver. A PSTN and conventional TV antenna interface is also provided.

Process for supplying video-on-demand and other requested programs and services from a headend

A simulation system is described for computing the overall signal generated in a substrate by a digital system comprising a plurality of gates associated with the substrate, wherein each gate is configured to perform a switching event. Output of a transistor-level model is compared with output of a lumped circuit model for each gate and the substrate, and signal contributions from each gate and switching event are determined based on the comparison. The system determines switching event signals for each of the plurality of gates. The signal contributions and the switching event signals are combined, and a combined lumped circuit model is derived based on a combination of lumped circuit models of the plurality of gates. The overall signal is computed based on the combined gate signal contributions and switching event signals, which are configured as an input to the combined lumped circuit model.

Method, apparatus and computer program product for determination of noise in mixed signal systems

The design of integrated circuits, i.e., semiconductor products, is made easier with a semiconductor platform having versatile power mesh that is capable of supporting simultaneous operations having different frequencies on the semiconductor product; e.g., higher frequency operations may be embedded as diffused blocks within the lower layers or may be programmed from a configurable transistor fabric above the diffused layers. Preferably the power mesh is located above the layers having the operations requiring the different frequencies, and may be fixed in an application set given to a chip designer or may be configurable by the designer her/himself. For example, to support high speed communications adjacent an embedded high speed data transceiver, the transistor fabric may be programmed as a data link layer having higher performance requirements than the rest of the integrated circuit. The data link layer may be connected to one of the localized grids of the versatile power mesh which may have an increased density and/or wider strap width of a power/ground grid. Additional decoupling capacitance can be embedded in the lower layers of the semiconductor product and/or can be programmed from the configurable transistors fabric.

Power mesh for multiple frequency operation of semiconductor products

A time to digital converter (TDC) has a pair of digital oscillators. The periods of the oscillators differ by TΔ. The oscillators are triggered by START and STOP pulses. A counter counts a number of pulses until reference points on the signals output by the oscillators coincide. Measurements may be made using a dual resolution method. Intrinsic jitter of the TDC can be determined by comparing sets of measurements in which the switch in resolutions is made at different points.

High resolution time-to-digital converter

An interconnect system between an integrated circuit device and a printed circuit board may include a filter between the integrated circuit device and the power subsystem of the printed circuit board. The filter may be a low-pass filter that reduces current in a higher frequency range without negatively modifying current in a lower frequency range and may reduce radiated emissions produced during operation of the integrated circuit. The filter may be implemented by arranging core-power voltage conductors and ground conductors at a first or second level interconnect into one or more voltage groupings and one or more adjacent ground groupings such that series inductance is increased. In some embodiments, the first level interconnect may include conductive bumps or pads between an integrated circuit and a substrate. In some embodiments, the second level interconnect may include solder balls, pins, pads, or other conductors of a package, socket, or interposer.

Interconnect design for reducing radiated emissions

An ASIC includes a PLL and digital circuitry to quantize and measure phase and average maximum jitter between a system clock input to the PLL, and a PLL-generated clock signal. The system clock is input to a series-string of delay elements, each contributing a delay of about 1Δt. Each delay element is associated with a two-input logic element, such as an EX-OR gate or an EX-NOR gate. One input to each two-input logic element is a version of the PLL-generated clock delayed by about (N/2) Δt. The second input to the first EX-OR is the output from the first delay element, the second input to the first EX-NOR is the output from the second delay element, and so on. Whichever delay element outputs a signal most closely in phase with the delayed PLL-generated clock will have an associated two-input logic element signal with a minimum duty cycle. Each two-input logic element output signal is capacitor integrated, sampled, stored and digitized. The digitized output signal identifies the lowest duty cycle two-input logic element, and thus phase shift. The relative breadth of the integrated capacitor voltage profile provides a measure of average maximum jitter.

On-chip PLL phase and jitter self-test circuit

A system and method for using a computer system to determine the desired decoupling components for stabilizing the electrical impedance in the power distribution system of an electrical interconnecting apparatus, including a method for measuring the ESR for an electrical device, a method for determining a number of desired decoupling components for a power distribution system, and a method for placing the desired decoupling components in the power distribution system. The method creates a model of the power distribution system based upon an M×N grid for both the power plane and the ground plane. The model receives input from a user and from a database of various characteristics for a plurality of decoupling components. The method determines a target impedance over a desired frequency range. The method selects decoupling components. The method determines a number for each of the decoupling components chosen. The method places current sources in the model at spatial locations corresponding to physical locations of active components. The method optionally also places a power supply in the model. The method selects specific locations in the model to calculate transfer impedance values as a function of frequency. The method effectuates the model to determine the transfer impedance values as the function of frequency at the specific locations previously chosen. The method then compares the transfer impedance values as the function of frequency at the specific locations to the target impedance for the power distribution system.

System and method for determining the desired decoupling components for power distribution systems using a computer system

A methodology for determining the placement of decoupling capacitors in a power distribution system and system therefor is disclosed. In one embodiment, a method for determining the placement of decoupling capacitors in a power distribution system includes determining target impedance, creating a power distribution system model, performing an LC (inductive-capacitive) resonance analysis, and performing a cavity resonance analysis. During the performance of the LC resonance analysis, capacitors may be selected in order to suppress impedance peaks resulting from LC resonances. Following the LC resonance analysis, the method may place the capacitors in the power distribution system at evenly spaced intervals. During the performance of the cavity resonance analysis, the capacitors may be repositioned in the power distribution system so as to suppress cavity resonances.

Methodology for determining the placement of decoupling capacitors in a power distribution system

A system and method for analyzing simultaneous switching noise In one embodiment, a model may be provided for the electronic circuit to be analyzed The electronic circuit may be an integrated circuit, a multi-chip module, a printed circuit assembly, or other type, and may in some embodiments include combinations of these types The electronic circuit may include a plurality of drivers, each of which may be coupled to a power plane, a ground plane, and a transmission line The connection of the driver may be accurately modeled in this manner Each driver may be configured to switch between a logic high voltage and a logic low voltage The modeled electronic circuit may also include a voltage source coupled to the power plane and the ground plane, a voltage regulator module, and a plurality of decoupling capacitors The simultaneous switching of a plurality of drivers, from a logic high to a logic low, or vice versa, may be simulated The system and method may then allow for the calculation of solutions for the transmission line and the power planes (as will be detailed below) The transmission line solution and power plane solution may be superimposed on each other, which may allow for an analysis of plane bounce, which may include one or more fluctuations in the voltage between the power plane and the ground planes

A system and method for analyzing simultaneous switching noise

A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide power to the integrated circuit. The power laminate may also include a voltage regulator circuit, and a plurality of decoupling capacitors.

Larry D. Smith

Papers

On-chip PLL phase and jitter self-test circuit

System and method for determining the desired decoupling components for power distribution systems using a computer system

Methodology for determining the placement of decoupling capacitors in a power distribution system

A system and method for analyzing simultaneous switching noise

Power distribution system with a dedicated power structure and a high performance voltage regulator