Interconnect has become a primary bottleneck in integrated circuit design As CMOS technology is scaled, it will become increasingly difficult for conventional copper interconnect to satisfy the design requirements of delay, power, bandwidth, and noise On-chip optical interconnect has been considered as a potential substitute for electrical interconnect in the past two decades In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-art optical technologies Electrical and optical interconnects are compared for various design criteria based on these predictions The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one tenth of the chip edge length at the 22 nm technology node

Predictions of CMOS compatible on-chip optical interconnect

This paper analyzes the impact of power-supply noise on the performance of high-frequency microprocessors. First, delay models that take this noise into account are proposed for device-dominated and interconnect-dominated timing paths. For typical circuits, it is shown that the peak of the noise is largely irrelevant and that the average supply voltage during switching is more important. It is then argued that global differential noise can potentially have a greater timing impact than common-mode noise. Finally, realistic values for the model parameters are measured on a 2.53-GHz Pentium4 microprocessor using a 130-nm technology. These values imply that the power-supply noise present on the system board reduces clock frequency by 6.7%. The model suggests that the frequency penalty associated with this power-supply noise will steadily increase and reach 7.6% for the 90-nm technology generation.

Impact of power-supply noise on timing in high-frequency microprocessors

A system may perform interconnect BIST (IBIST) testing on source synchronous links. More particularly, the system may perform, at normal operating frequency for the source synchronous link, a source synchronous link test that tests a victim line on the source synchronous link using a transition weave pattern. The transition weave pattern causes interaction between a data transition on the victim line, previous transitions on the victim line, and transitions on the other lines of the link (the 'aggressor' lines). The interaction caused may be: (i) a first crossing pulse on the victim line; (ii) a second crossing pulse of the opposite polarity on each aggressor line concurrent with the first crossing pulse on the victim line; and (iii) a reflection in the opposite direction of the first transition of the first crossing pulse, wherein the reflection results from a previous transition on the victim line. Additionally, in one embodiment, the system may perform repeated iterations of the transition weave pattern while varying the timing of the previous transition on the victim line (to create the reflection) with respect to the first crossing pulse on the victim line.

Source synchronous link integrity validation

Variations of power and ground levels affect very large scale integration circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the presence of uncorrelated power and ground noise. In this paper, we analyze the effect of such noise-on-signal propagation through a buffer and present simple, closed-form formulas to estimate the corresponding change of delay. The model captures both positive (slowdown) and negative (speedup) delay changes. It is consistent with short-channel MOSFET behavior, including carrier velocity saturation effects. An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply-level-induced jitter characteristics. The expressions can be used in any existing circuit performance optimization design flow or can be combined into any delay calculations as a correction factor.

/pdf/buffer-delay-change-in-the-presence-of-power-and-ground-40vh31hglx.pdf

Buffer delay change in the presence of power and ground noise

The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has typically applied a worst case voltage drop at all points along a circuit path which leads to a very conservative analysis. We also show that in certain cases, the traditional analysis can be optimistic, since it ignores the possibility of voltage shifts between driver and receiver gates. In this paper, we propose a new analysis approach for computing the maximum path delay under power supply fluctuations. Our analysis is based on the use of superposition, both spatially across different circuit blocks, and temporally in time. We first present an accurate model of path delay variations under supply drops, considering both the effect of local supply reduction at individual gates and voltage shifts between driver/receiver pairs. We then formulate the path delay maximization problem as a constrained linear optimization problem, considering the effect of both IR drop and LdI/dt drops. We show how correlations between currents of different circuit blocks can be incorporated in this formulation using linear constraints. The proposed methods were implemented and tested on benchmark circuits, including an industrial power supply grid and we demonstrate a significant improvement in the worst-case path delay increase.

/pdf/vectorless-analysis-of-supply-noise-induced-delay-variation-39gihkr602.pdf

Vectorless Analysis of Supply Noise Induced Delay Variation

Variation of power and ground levels affect VLSI circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the presence of uncorrelated power and ground noise. In this paper, we analyze the effect of such noise on signal propagation through a buffer and present simple, closed-form formulas to estimate the corresponding change of delay. The model captures both positive (slowdown) and negative (speedup) delay changes. It is consistent with short-channel MOSFET behavior, including carrier velocity saturation effects. An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply level-induced jitter characteristics.

/pdf/coping-with-buffer-delay-change-due-to-power-and-ground-4z82yd2fgl.pdf

Coping with buffer delay change due to power and ground noise

In this paper we study signal alignment resulting in maximum peak interconnect crosstalk noise. We consider two cases. In the first one we assume that arbitrary arrival times of input signals are feasible. In the second case we assume that timing windows are given for each aggressor input. We propose a simple procedure to find aggressor alignment for worst-case coupling in both cases.

/pdf/aggressor-alignment-for-worst-case-coupling-noise-20jhnyrcki.pdf

Aggressor alignment for worst-case coupling noise

In this paper we present efficient closed-form formulas to estimate the incremental delay change induced by capacitive interconnect coupling. We also analyze temporal correlations among switching signals and develop criteria for timing window alignment. Our approximations are conservative and yet achieve acceptable accuracy. The formulas are simple enough to be used in the inner loops of static timing analysis.

/pdf/incremental-delay-change-due-to-crosstalk-noise-3ytz98g4yx.pdf

Incremental delay change due to crosstalk noise

In this paper we present efficient closed-form formulas to estimate capacitive coupling-induced delay in distributed RC coupling networks. The efficiency of our approach stems from the fact that only five basic operations are used in the expressions: addition (x + y), subtraction (x − y), multiplication (x × y), division (x / y) and square root (\sqrt{x}). The formulas do not require exponent computation or numerical iterations. Our estimates, though conservative, achieve acceptable accuracy. They are simple enough to be used in the inner loops of performance optimization or as cost functions for a router. The delay expressions capture the dependency on coupling direction and coupling location (near-driver and near-receiver).

Lauren Hui Chen

Papers

Buffer delay change in the presence of power and ground noise

Coping with buffer delay change due to power and ground noise

Aggressor alignment for worst-case coupling noise

Incremental delay change due to crosstalk noise

Closed-Form Crosstalk Noise Delay Metrics