In this paper the analysis of DRAM logic compatible 3T cell has been shown. Due to its high density and low cost of memory, it is universally used by the advanced processor for on chip data and program memory. DRAM has transistor-capacitor cell structure, where capacitor is charged to produce 1 or 0. Memory array, which is arranged in row and column, is word line and bit line respectively. Here I have proposed sleep transistor technique at 3T dram with semantic design, for improvement of leakage and also calculated stability by calculating noise, slew rate and settling time. This circuit proposed two voltage source are connected to bit line and bit line bar respectively. Switching of main transistor is performed by word line, which is at low for write operation and high for read operation. The simulation result shows that when a wide range of operating voltage is taken, which is from 0.7 to 1.3v then it is observed that low voltage operation is suitable for low slew rate or low read access time and the leakage current reduced as increase in the range of operating voltage. At 0.7v the leakage current is 595.4×10-12 amp, slew rate is 6.96×103 dB, noise measurement is 5.995×10-14, settling time is 46.63×10-9. The design has been carried out at the 45 nanometre scale technology on cadence virtuoso simulating tool.

Reduction of Leakage Power a Noise for DRAM Design Using Sleep Transistor Technique

The demand for low power devices is increasing vastly due to the fast growth of battery operated applications such as smart phones and other handheld devices. It has become important to control the power dissipation throughout the design cycle beginning from the architectural level to final design at hardware level. Leakage current is the main factor which contributes to almost or more than 50% of total power dissipation. In many new high performance designs, the leakage component of power consumption is comparable to the switching component. More than 40% leakage in SRAM memory is due to leakage in transistors. This survey paper use the design of SRAM architecture to reduce the leakage current and hence the leakage power. The various leakage power reduction techniques have been evolved to tackle the problem and it is still in progress. In this paper mainly, there is study of various leakage power reduction techniques with SRAM architecture in fabrication Technology.

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Leakage power reduction technique in cmos circuit: a state-of-the-art review

As process technology shrinks, the adaptive leakage power compensation scheme will become more important in realizing high-performance and low-power applications. In order to minimize total active power consumption in digital circuits, one must take into account sub-threshold leakage currents that grow exponentially as technology scales. This describes to predict how dynamic power and sub-threshold power must be balanced. The exclusive supply voltage control switching makes stable operations. The threshold voltage control successfully maintains a ratio of switching to leakage current and which represents the reduced power consumption. The goal of this paper is to: i) Maintains the optimized body bias conditions. ii) Maintains the best power-delay tradeoff. The results with a 180-nm CMOS device explain that the proposed architecture causes in the successful optimization of power.

/pdf/implementation-of-delay-and-power-monitoring-schemes-to-4votmt95na.pdf

Implementation of Delay and Power Monitoring Schemes to Reduce the Power Consumption

With the improved technological development of large ICs, system designers characterized the circuit by reliability, low power dissipation, power consumption, chip density and leakage current. The designers were required to reduce each of these for improved performance, reduced cost and chip size area. CMOS technology increased in level of importance to the point where it now clearly holds the center stage as the dominant VLSI technology. The advanced memories provides considerable capability and extensive application. The main memory is usually of the dynamic random access type. These are highly dense memories with high data storage capability. The major limitation of this memory type is that it losses its data due to the discharge of capacitor and current leakage across the transistors. Thus, they are provided with external refresh circuitry to hold the data increasing the power consumption correspondingly. In this paper we are implementing a low power 4×4 DRAM (Dynamic Random Access Memory) with Self Controllable Voltage Level (SCVL) technique to reduce the leakage current in the design. Simulation is done by using Microwind and DSCH 2.

A 0.25µm SCVL based 4T DRAM design for minimizing leakage current using CMOS technology

Memory is the basic need of most of the electronic devices. These memories are mainly designed using CMOS transistors. As we talk about CMOS transistors power, area and speed of each transistor is a major issue of concern. But we know that there is a trade-off between these three factors. Still engineers and researchers are working upon these issues. Issue arises when we switch to lower technologies as within the same die area we have to implant more number of transistors which leads to high chip density and thus high parasitic capacitance. Scaling of transistors is another factor. Thus in this paper we will study about various works done in reducing power dissipation in 5T SRAM cell using different methods in different technologies, a bit compromising in area and speed.

Survey On Various Works Done In Reducing Static Power In Various SRAM Cells

In present trend of integration will continue in the projected future. When comparing the integration density of integrated circuits, a clear distinction must be made between the memory chips and logic chips. Memory circuits are highly regular. Increase of chip complexity is consistently higher for memory circuits. The salient features such as low power, reliable performance, circuit techniques for high speed such as using dynamic circuits, and low leakage current, most of these have get give a better advantage. This paper gives an idea about 4T DRAM (dynamic random access memory) which is implemented by using a self controllable voltage level technique. In this technique reduces the leakage current and produce the high performance. Simulation is done by using a microwind 3.1 and DSCH3. Using a 90 nm technology to implemented a 4T DRAM. By using this give the benefit of 67% reduction of leakage current. This reduction gives a advantage of high performance and low leakage current, by controlling these parameter speed is automatically increase.

http://iasir.net/IJETCASpapers/IJETCAS12-375.pdf

4T DRAM based on Self-controllable Voltage Level technique for low leakage power in VLSI

As the technology improved to support very large chip sizes, system designers were faced with power consumption problem and leakage current problem. CMOS technology has increased in level of importance to the point where it now clearly holds center stage as the dominant VLSI technology In this research paper shows the implementation of a DRAM 4×4 (dynamic random access memory) with self controllable voltage level (SVL) technique. SVL technique is leakage current reduction technique. Simulation is done by using a microwind 3.1 and DSCH 2. By using a SVL technique in DRAM 4×4, 37% of leakage current is reduced.

Laxmi Singh

Papers

4T DRAM based on Self-controllable Voltage Level technique for low leakage power in VLSI

Used self-controllable voltage level technique to reduce leakage current in DRAM 4×4 in VLSI