Proceedings ArticleDOI
Used self-controllable voltage level technique to reduce leakage current in DRAM 4×4 in VLSI
Laxmi Singh,Ajay Somkuwar +1 more
- pp 346-351
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TLDR
This research paper shows the implementation of a DRAM 4×4 (dynamic random access memory) with self controllable voltage level (SVL) technique, which is leakage current reduction technique.Abstract:
As the technology improved to support very large chip sizes, system designers were faced with power consumption problem and leakage current problem. CMOS technology has increased in level of importance to the point where it now clearly holds center stage as the dominant VLSI technology In this research paper shows the implementation of a DRAM 4×4 (dynamic random access memory) with self controllable voltage level (SVL) technique. SVL technique is leakage current reduction technique. Simulation is done by using a microwind 3.1 and DSCH 2. By using a SVL technique in DRAM 4×4, 37% of leakage current is reduced.read more
Citations
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Journal ArticleDOI
Implementation of Delay and Power Monitoring Schemes to Reduce the Power Consumption
Naidu. K Jagannadha,V Nagaraju. +1 more
TL;DR: The goal of this paper is to maintain the optimized body bias conditions and achieve the best power-delay tradeoff in dynamic power and sub-threshold power.
Proceedings ArticleDOI
A 0.25µm SCVL based 4T DRAM design for minimizing leakage current using CMOS technology
Sarang Kulkarni,Neha Rai +1 more
TL;DR: A low power 4×4 DRAM (Dynamic Random Access Memory) with Self Controllable Voltage Level (SCVL) technique to reduce the leakage current in the design.
Book ChapterDOI
Study and Analysis of Retention Time and Refresh Frequency in 1T1C DRAM at Nanometer Regime
Amol S. Sankpal,D. J. Pethe +1 more
TL;DR: In this article, the performance analysis of 1T1C DRAM cell is affected due to various leakage sources in MOS transistor, the leakage current, leakage power, retention time and refresh frequency (Frefresh) were investigated.
References
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PRINCIPLES OF CMOS VLSI DESIGN A Systems Perspective Second Edition
Neil Weste,Kamran Eshraghian +1 more
Abstract: Introduction to CMOS Circuits. Introduction. MOS Transistors. MOS Transistor Switches. CMOS Logic. Circuit Representations. CMOS Summary. MOS Transistor Theory. Introduction. MOS Device Design Equation. The Complemenatry CMOS Inverter-DC Characteristics. Alternate CMOS Inverters. The Differential Stage. The Transmission Gate. Bipolar Devices. CMOS Processing Technology. Silicon Semiconductor Technology: An Overview. CMOS Technologies. Layout Design Rules. CAD Issues. Circuit Characterization and Performance Estimation. Introduction. Resistance Estimation. Capacitance Estimation. Inductance. Switching Characteristics. CMOS Gate Transistor Sizing. Power Consumption. Determination of Conductor Size. Charge Sharing. Design Margining. Yield. Scaling of MOS Transistor Dimensions. CMOS Circuit and Logic Design. Introduction. CMOS Logic Structures. Basic Physical Design of Simple Logic Gates. Clocking Strategies. Physical and Electrical Design of Logic Gates. 10 Structures. Structured Design Strategies. Introduction. Design Economics. Design Strategies. Design Methods. CMOS Chip Design Options. Design Capture Tools. Design Verification Tools. CMOS Test Methodolgies. Introduction. Fault Models. Design for Testability. Automatic Test Pattern Generation. Design for Manufacturability. CMOS Subsystem Design. Introduction. Adders and Related Functions. Binary Counters. Multipliers and Filter Structures. Random Access and Serial Memory. Datapaths. FIR and IIR Filters. Finite State Machines. Programmable Logic Arrays. Random Control Logic.
Journal ArticleDOI
Statistical analysis of subthreshold leakage current for VLSI circuits
TL;DR: An analytical expression is derived to estimate the probability density function of the leakage current for stacked devices found in CMOS gates and an approach is presented to account for both the inter- and intra-die gate length variations to ensure that the circuit leakage PDF correctly models both types of variation.
Journal ArticleDOI
Gate oxide leakage current analysis and reduction for VLSI circuits
TL;DR: A fast approach to analyze the total leakage power of a large circuit block, considering both I/sub gate/ and subthreshold leakage (I/sub sub/), and proposes the use of pin reordering as a means to reduce I/ sub gate/.
Journal ArticleDOI
A combined gate replacement and input vector control approach for leakage current reduction
TL;DR: A divide-and-conquer approach is presented that integrates gate replacement, an optimal MLV searching algorithm for tree circuits, and a genetic algorithm to connect the tree circuits to overcome the limitation of internal gates at high logic levels.