An insulated-gate semiconductor device, such as an IGFET or IGT, with improved source-to-base shorts includes, in a semiconductor wafer, a drain region, a voltage-supporting region, a base region, and a source region. Generally parallel gate fingers of refractory material are insulatingly spaced above the wafer. Elongated base portions are provided between, and preferably registered to, a respective pair of adjacent gate fingers. Elongated source portions are each situated within a respective base portion and each is preferably registered to a respective pair of adjacent gate fingers. Generally parallel shorting portions are included in the wafer and are oriented transverse to the gate fingers, whereby the shorting portions can be formed without a critical alignment step. The shorting portions adjoin the base portions and also a source electrode so as to complete source-to-base electrical shorts. Parasitic majority current carriers in the base portions are readily drawn into the shorting portions, which are preferably situated very close to each other and, then, are conducted to the source electrode. Accordingly, the shorting portions are highly effective at reducing parasitic currents in the device.

Method of making an insulated-gate semiconductor device with improved shorting region

The method includes providing a semiconductor chip having a first main face and a second main face opposite the first main face. The semiconductor chip includes an electrical device adjacent to the first main face. Material of the semiconductor chip is removed at the second main face except for a pre-defined portion so that a non-planar surface remains at the second main face.

Method of Manufacturing a Semiconductor Device

A method for the production of metal-semiconductor field effect transistors (MESFET) is described. Practice of the method allows one to produce self-aligning MESFETs with Si sources and drains in close proximity having metal gates therebetween.

Method of fabrication of self-aligned metal-semiconductor field effect transistors

An imager having gates with spacers formed of a high dielectric material. The high dielectric spacer provides larger fringing fields for charge transfer and improves image lag and charge transfer efficiency.

High dielectric constant spacer for imagers

Method for producing a bipolar transistor utilizing an oxidized semiconductor masking layer in conjunction with an anti-oxidation mask

This abstract describes a process of construction of an Nchannel charge coupled device. It provides a step-by-step series of operations which will produce on a P-type substrate of silicon a series of interposed spaced polysilicon gates and aluminum gates. The polysilicon gates are deposited on a thin silicon nitrade layer which is positioned on a thin silicon oxide layer, both of minimum thickness, so there is good capacitive coupling between the polysilicon and the silicon. A thick layer of silicon oxide is formed over the polysilicon gate, after which the nitride layer between the polysilicon gates is etched away. A silicon oxide layer is deposited in the space between the nitride areas and on top of that an aluminum gate is deposited. Conventional means are provided to attach conductor leads to the polysilicon gates. If desired Boron or other elements can be implanted in the silicon before the oxide and aluminum gates are deposited.

Leonard Forbes

Papers

N-Channel charge coupled device fabrication process