New high-speed VLSI architectures for decoding Reed-Solomon codes with the Berlekamp-Massey algorithm are presented in this paper. The speed bottleneck in the Berlekamp-Massey algorithm is in the iterative computation of discrepancies followed by the updating of the error-locator polynomial. This bottleneck is eliminated via a series of algorithmic transformations that result in a fully systolic architecture in which a single array of processors computes both the error-locator and the error-evaluator polynomials. In contrast to conventional Berlekamp-Massey architectures in which the critical path passes through two multipliers and 1+[log/sub 2/,(t+1)] adders, the critical path in the proposed architecture passes through only one multiplier and one adder, which is comparable to the critical path in architectures based on the extended Euclidean algorithm. More interestingly, the proposed architecture requires approximately 25% fewer multipliers and a simpler control structure than the architectures based on the popular extended Euclidean algorithm. For block-interleaved Reed-Solomon codes, embedding the interleaver memory into the decoder results in a further reduction of the critical path delay to just one XOR gate and one multiplexer, leading to speed-ups of as much as an order of magnitude over conventional architectures.

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High-speed architectures for Reed-Solomon decoders

This paper presents high-speed parallel Reed-Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high-speed multigigabit-per-second fiber optic systems. Pipelining and parallelizing allow inputs to be received at very high fiber-optic rates and outputs to be delivered at correspondingly high rates with minimum delay. A parallel processing architecture results in speed-ups of as much as or more than 10 Gb, since the maximum achievable clock frequency is generally bounded by the critical path of the modified Euclidean algorithm block. The parallel RS decoders have been designed and implemented with the 0.13-/spl mu/m CMOS standard cell technology in a supply voltage of 1.1 V. It is suggested that a parallel RS decoder, which can keep up with optical transmission rates, i.e., 10 Gb/s and beyond, could be implemented. The proposed channel = 4 parallel RS decoder operates at a clock frequency of 770 MHz and has a data processing rate of 26.6 Gb/s.

High-speed VLSI architecture for parallel Reed-Solomon decoder

In this tutorial paper, we present the application of well-known DSP techniques used in lower speed wireline and wireless applications, to high-speed optical communications. After an introduction on today's optical network architecture and typical optical channel impairments, we study techniques such as fiber equalization, maximum likelihood detection, and current and next generations Forward Error Correction (FEC), with special emphasis on VLSI implementation.

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Equalization and FEC techniques for optical transceivers

Current key initiatives in deep-space optical communications are treated in terms of historical context, contemporary trends, and prospects for the future An architectural perspective focusing on high-level drivers, systems, and related operations concepts is provided Detailed subsystem and component topics are not addressed A brief overview of past ideas and architectural concepts sets the stage for current developments Current requirements that might drive a transition from radio frequencies to optical communications are examined These drivers include mission demand for data rates and/or data volumes; spectrum to accommodate such data rates; and desired power, mass, and cost benefits As is typical, benefits come with associated challenges For optical communications, these include atmospheric effects, link availability, pointing, and background light The paper describes how NASA's Space Communication and Navigation Office will respond to the drivers, achieve the benefits, and mitigate the challenges, as documented in its Optical Communications Roadmap Some nontraditional architectures and operations concepts are advanced in an effort to realize benefits and mitigate challenges as quickly as possible Radio frequency communications is considered as both a competitor to and a partner with optical communications The paper concludes with some suggestions for two affordable first steps that can yet evolve into capable architectures that will fulfill the vision inherent in optical communications

Deep-space optical communications

A method and system for mitigating and compensating for loss of digital audio data transmitted as a stream of packets to a client (30). A server (10) compresses digital audio data corresponding to a digitized analog audio signal. The compressed data are divided into N frames of data per packet. The server interleaves the frames, producing interleave packets of up to order N. The interleave operation minimizes the effect of any lost packet when the interleave packets are received, deinterleaved, and converted to an analog signal that is played on a speaker at the client. Lost frames are replaced using the data from frames that are received. As a further aspect, the frames can be scrambled at the server by applying a permutation function F that depends upon the packet number (PN) and a Key value. At the client, an inverse permutation function F-1 is applied to unscramble the frames.

Error mitigation and correction in the delivery of on demand audio

A pipeline structure of a transform decoder similar to a systolic array is developed to decode Reed-Solomon (RS) codes. The error locator polynomial is computed by a modified Euclid's algorithm which avoids computing inverse field elements. The new decoder is regular and simple, and naturally suitable for VLSI implementation.

A VLSI design of a pipeline Reed-Solomon decoder

A concatenated coding system consisting of a (255,223) Reed-Solomon outer code and a convolutional inner code is provided with either a block of preinterleaved frames or an interleaver of frames in a block of data symbols to be coded in the outer decoder. By interleaving, errors are constrained to occur in only one symbol in a frame, which can be corrected by the Reed-Solomon outer decoder. After transmission and inner decoding, the data symbols are deinterleaved for outer decoding. Instead of preinterleaving at the source, or interleaving before inner encoding, the frames of data symbols may be interleaved at the receiver after inner decoding and then combined with the inner decoded check symbols for outer decoding. The outer encoder is a bit-serial Reed-Solomon encoder with programmable interleaving, and the inner decoder is a Viterbi decoder.

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VLSI single-chip (255,223) Reed-Solomon encoder with interleaver

Two pipeline (255,233) RS decoders, one a time domain decoder and the other a transform domain decoder, use the same first part to develop an errata locator polynomial τ(x), and an errata evaluator polynominal A(x). Both the time domain decoder and transform domain decoder have a modified GCD that uses an input multiplexer and an output demultiplexer to reduce the number of GCD cells required. The time domain decoder uses a Chien search and polynomial evaluator on the GCD outputs τ(x) and A(x), for the final decoding steps, while the transform domain decoder uses a transform error pattern algorithm operating on τ(x) and the initial syndrome computation S(x), followed by an inverse transform algorithm in sequence for the final decoding steps prior to adding the received RS coded message to produce a decoded output message.

/pdf/architecture-for-time-or-transform-domain-decoding-of-reed-2dnr35h86n.pdf

Architecture for time or transform domain decoding of reed-solomon codes

A next-generation deep-space network is currently under consideration by the National Aeronautics and Space Administration. Building upon its many past successes, this network will be required to meet the needs of current and planned missions. These will, no doubt, include the familiar suite of telemetry, command, tracking, and navigation services, with performance levels derived from analysis of the probable future mission set. Additionally, it will be expected to provide enabling capabilities for missions still on the drawing boards. Traditionally, the network serves the robotic deep-space exploration fleet. However, at this time, consideration of the special needs of planned future human lunar missions is appropriate, as well as the evolution to the eventual human exploration of Mars.

Prospects for a Next-Generation Deep-Space Network

The National Aeronautics and Space Administration (NASA) Exploration Systems Mission Directorate is planning a series of human and robotic missions to the Earth's Moon and to Mars. These missions will require telecommunication and navigation services. This paper sets forth presumed requirements for such services and presents strawman lunar and Mars telecommunications network architectures to satisfy the presumed requirements. The paper suggests that a modest ground network would suffice for missions to the near-side of the Moon. A constellation of three Lunar Telecommunications Orbiters connected to a modest ground network could provide continuous redundant links to a polar lunar base and its vicinity. For human and robotic missions to Mars, a pair of areostationary satellites could provide continuous redundant links between a mid-latitude Mars base and Deep Space Network antennas augmented by large arrays of 12-m antennas

Leslie J. Deutsch

Papers

A VLSI design of a pipeline Reed-Solomon decoder

VLSI single-chip (255,223) Reed-Solomon encoder with interleaver

Architecture for time or transform domain decoding of reed-solomon codes

Prospects for a Next-Generation Deep-Space Network

Integrated network architecture for sustained human and robotic exploration