Li Zhao

TL;DR: Detailed simulations with server workloads show that filter-based DRAM caching techniques achieve the following: on average over 30% performance improvement over previous solutions, several magnitudes lower area overhead in tag space required for cache-line based DRAM caches, and significantly lower memory bandwidth consumption as compared to page-granularDRAM caches.

TL;DR: This paper investigates a framework that would be needed for a CMP to fully provide QoS, and proposes novel throughput optimization techniques that include: exploiting various QoS execution modes, and a microarchitecture technique that steals excess resources from a job while still meeting its QoS target.

TL;DR: This paper describes research challenges and introduces a heterogeneous prototype platform called QuickIA that enables rapid exploration of heterogeneous architectures employing multiple generations of Intel processors for evaluating the implications of asymmetry and FPGAs to experiment with specialized processors or accelerators.

TL;DR: A detailed description of the anatomy of a secure session is presented and the time spent on the various cryptographic operations (symmetric, asymmetric and hashing) during the session negotiation and data transfer is analyzed.

TL;DR: This article presents NePSim, an integrated system that includes a cycle-accurate architecture simulator, an automatic formal verification engine, and a parameterizable power estimator for NPs consisting of clusters of multithreaded execution cores, memory controllers, I/O ports, packet buffers, and high-speed buses.