This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

On-chip frequency generators for high frequency applications suffer from degradation of key passive components, variable capacitors in particular. In this framework, frequency multipliers can play a key role, allowing the design of voltage-controlled oscillators running at a frequency lower than required with advantage in terms of signal spectral purity and frequency tuning range. In this paper we present two injection locked frequency doublers for Ku-band and F-band applications respectively. Despite differences in implementation details, the same topology where a push-push pair injects a double frequency tone locking an autonomous differential oscillator is adopted. The circuits require limited input signal swing and provide a differential output over a broad frequency range. Dissipating 5.2 mW, the Ku-band multiplier, realized in a 0.13 μm CMOS node, displays an operation bandwidth from 11 GHz to 15 GHz with a peak voltage swing on each output of 470 mV. The F-band multiplier, realized in 65 nm CMOS technology, displays an operation bandwidth from 106 GHz to 128 GHz with a peak voltage swing on each output of 330 mV and a power dissipation of 6 mW. A prototype including the multiplier, driven by a half-frequency standard LC-tank VCO, demonstrates an outstanding 13.1 % tuning range around 115 GHz.

Injection-Locked CMOS Frequency Doublers for μ-Wave and mm-Wave Applications

We propose an aqueous functionalized molybdenum disulfide nanoribbon suspended over a solid electrode as a capacitive displacement sensor aimed at determining the DNA sequence. The detectable sequencing events arise from the combination of Watson–Crick base-pairing, one of nature’s most basic lock-and-key binding mechanisms, with the ability of appropriately sized atomically thin membranes to flex substantially in response to subnanonewton forces. We employ carefully designed numerical simulations and theoretical estimates to demonstrate excellent (79% to 86%) raw target detection accuracy at ∼70 million bases per second and electrical measurability of the detected events. In addition, we demonstrate reliable detection of repeated DNA motifs. Finally, we argue that the use of a nanoscale opening (nanopore) is not requisite for the operation of the proposed sensor and present a simplified sensor geometry without the nanopore as part of the sensing element. Our results, therefore, potentially suggest a real...

A MoS2-Based Capacitive Displacement Sensor for DNA Sequencing.

Reliability of communications is key to expand application domains for sensor networks. Since Wireless Sensor Networks (WSN) operate in the license-free Industrial Scientific and Medical (ISM) bands and hence share the spectrum with other wireless technologies, addressing interference is an important challenge. In order to minimize its effect, nodes can dynamically adapt radio resources provided information about current spectrum usage is available.We present a new channel quality metric, based on availability of the channel over time, which meaningfully quantifies spectrum usage. We discuss the optimum scanning time for capturing the channel condition while maintaining energy-efficiency. Using data collected from a number of Wi-Fi networks operating in a library building, we show that our metric has strong correlation with the Packet Reception Rate (PRR). This suggests that quantifying interference in the channel can help in adapting resources for better reliability. We present a discussion of the usage of our metric for various resource allocation and adaptation strategies.

/pdf/quantifying-the-channel-quality-for-interference-aware-e1dworrjqs.pdf

Quantifying the channel quality for interference-aware wireless sensor networks

Realizations of voltage-mode and current-mode complex filters based on transconductance, transresistance, and current amplifiers for intermediate frequency (IF) applications are systematically developed. Various amplifiers are realized utilizing the second generation current conveyor (CCII) to promote comparisons at device levels. The adopted approach shows that the most efficient designs in terms of the number of active components are current-mode filters based on the transconductance and current amplifiers. As an application example, a 4th-order complex filter based on the CA is designed for low-IF Bluetooth receiver. Fabricated in a standard 0.18 μm CMOS technology, experimental results show that the proposed design offers improved characteristics over the available solutions in terms of power consumption and spurious-free dynamic range (SFDR). The filter exhibits in-band SFDR of 65.8 dB while consuming 1 mW.

/pdf/optimal-low-power-complex-filters-2gvk5nphoj.pdf

Optimal Low Power Complex Filters

A new high performance charge pump circuit is designed and realized in 0.18 m CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range. Furthermore, a method of adding a precharging current source is proposed to increase the initial charge current, which will speed up the settling time of CPPLLs. Test results show that the current mismatching can be less than 0.4% in the output voltage range of 0.4 to 1.7 V, with a charge pump current of 100 A and a precharging current of 70 A. The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.

https://iopscience.iop.org/article/10.1088/1674-4926/32/7/075007/pdf

Design of a high performance CMOS charge pump for phase-locked loop synthesizers

This paper presents a low-power low-IF RF frontend for 2.4GHz wireless sensor networks (WSN) in 0.18μm RF CMOS technology. The RF frontend consists of a variable gain low noise amplifier (VG-LNA), a quadrature passive mixer and a divide-by-two circuit which generates the differential quadrature LO signals for quadrature balanced mixer. The effect of the input parasitic capacitance on the inductively degenerated common source LNA's input impedance is analyzed in detail. An external LC network was used to achieve input matching under low power consumption. The proposed VG-LNA has three gain modes: high gain, medium gain and low gain modes. The gain control function can accommodate a high input level and satisfy the need dynamic range of WSN. The passive mixer shows high linearity, low 1/f noise and near zero power consumption. The measurement results of the frontend achieve 15dB voltage conversion gain, 4dB noise figure at the high gain mode, −1.5dBm input third order intercept point at the low gain mode, while the DC power consumption is 10.4 mW under a 1.8V supply voltage.

A 2.4GHz low-IF RF frontend for wireless sensor networks

A Gm?C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 ?m CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors. A conventional phase-locked loop is used to realize the on-chip automatic tuning for both center frequency and bandwidth control. The filter is centered at 2 MHz with a bandwidth of 2.4 MHz. The measured results show that the filter provides more than 45 dB image rejection while the ripple in the pass-band is less than 1.2 dB. The complete filter including on-chip tuning circuit consumes 4.9 mA with 1.8 V single supply voltage.

https://iopscience.iop.org/article/10.1088/1674-4926/32/5/055002/pdf

A CMOS G m – C complex filter with on-chip automatic tuning for wireless sensor network application

The design, implementation, and characterization of an image-rejection double quadrature conversion mixer based on RC asymmetric polyphase filters (PPF) are presented. The mixer consists of three sets of PPFs and a mixer core for quadrature down conversion. Two sets of PPFs are used for the quadrature generation and the other one is used for the IF signal selection to reject the unwanted image band. Realized in 0.18-μm CMOS technology as a part of the DVB-T receiver chip, the mixer exhibits a high image rejection ratio (IRR) of 58 dB, a power consumption of 11 mW, and a 1-dB gain compression point of −15 dBm.

http://iopscience.iop.org/article/10.1088/1674-4926/30/6/065003/pdf

A CMOS image-rejection mixer with 58-dB IRR for DTV receivers

A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented. The divider based on a dual-modulus prescaler (DMP) and pulse-swallow counter is designed to reduce power consumption and chip area. Implemented in the 0.18-μm mixed-signal CMOS process, the divider operates over a wide range of 1–7.4 GHz with an input signal of 7.5 dBm; the programmable divider output phase noise is −125.3 dBc/Hz at an offset of 100 kHz. The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm2. The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.

http://iopscience.iop.org/article/10.1088/1674-4926/31/5/055004/pdf

Li Zhiqun

Papers

Design of a high performance CMOS charge pump for phase-locked loop synthesizers

A 2.4GHz low-IF RF frontend for wireless sensor networks

A CMOS G m – C complex filter with on-chip automatic tuning for wireless sensor network application

A CMOS image-rejection mixer with 58-dB IRR for DTV receivers

A 5-GHz programmable frequency divider in 0.18-μm CMOS technology