Quantisation is a key optimisation strategy to improve the performance of floating-point deep neural network (DNN) accelerators. Digital signal processing (DSP) blocks on field-programmable gate arrays are not efficiently utilised when the accelerator precision is much lower than the DSP precision. Through three modifications to Xilinx DSP48E2 DSP blocks, we address this issue for important computations in embedded DNN accelerators, namely the standard, depth-wise, and pointwise convolutional layers. First, we propose a flexible precision, run-time decomposable multiplier architecture for CNN implementations. Second, we propose a significant upgrade to DSPDSP interconnect, providing a semi-2D low precision chaining capability which supports our low-precision multiplier. Finally, we improve data reuse via a register file which can also be configured as FIFO. Compared with the 27 × 18-bit mode in the Xilinx DSP48E2, our Precision, Interconnect, and Reuseoptimised DSP (PIR-DSP) offers a 6× improvement in multiplyaccumulate operations per DSP in the 9 × 9-bit case, 12× for 4 × 4 bits, and 24× for 2 × 2 bits. We estimate that PIR-DSP decreases the run time energy to 31/19/13% of the original value in a 9/4/2-bit MobileNet-v2 DNN implementation.

PIR-DSP: An FPGA DSP Block Architecture for Multi-precision Deep Neural Networks

A self-timed pulsed latch (STPL) is proposed for low $V_{\mathrm {DD}}$ operation. By comparing input and output, the transparency window is adaptively generated in STPL, which resolves the hold time problem of the conventional pulsed latch. The measurement results from the test chip fabricated in the 65-nm technology proves that the hold time is reduced by 77% and the minimum operating supply voltage is lowered by 300 mV compared with the conventional pulsed latch. In addition, the measurement results show that the STPL can reduce the sequential overhead, because the STPL is free from setup time issue from which the conventional master–slave-based flip-flop (MSFF) suffers. The simulation results show that the input-to-output delay of STPL, which also determines the sequential overhead, is smaller by 45% in 0.6 V compared with that of the MSFF structure.

Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time

Design and analysis of ultra-low power 18T adaptive data track flip-flop for high-speed application

Summary

Two novel low power and high-speed pulse triggered flip-flops were presented in this paper. Short circuit current was controlled, and race condition between pull-up and pull-down branches was removed, which caused reduction of power consumption. On the other hand, the number of stack transistors in the discharging path was reduced which decreased delay of the flip-flops. The first proposed flip-flop reduced the number of transistors and the second proposed flip-flop used conditional data mapping and removed floating node of the first flip-flop. Post-layout simulation result showed that the first proposed flip-flop reduced 21% of power delay product and the second proposed flip-flop reduced 16% of power delay product in comparison with other flip-flops in 50% of data switching activities. Copyright © 2014 John Wiley & Sons, Ltd.

Two novel low power and very high speed pulse triggered flip‐flops

Energy-constrained microprocessor design plays an important role in many emerging Internet of Things platforms operating on harvested or limited energy budget. For this purpose, operating at the supply voltage corresponding to the minimum energy point (MEP) can achieve significant energy savings. However, the MEP voltage is highly dependent on the threshold voltage, the structure, and the activity rate of the circuit. This is more pronounced in pipelined processors as different pipeline stages have different structure with huge intrinsic activity rate variations. Therefore, the energy-saving is limited when only a single MEP voltage is chosen for the entire microprocessor. To address this issue, we propose a fine-grained MEP tuning technique, in which the individual pipeline stages are designed to operate at their MEPs, through per pipeline stage supply and threshold voltage tuning, by considering their activity rates. The proposed optimization is applied to two processors, FabScalar and OpenSPARC, and simulation results show that the proposed technique can improve the energy efficiency of both the cores by almost 50%. The improvement in energy efficiency is obtained at the cost of 6% performance and < 2% area overhead.

Fine-Grained Energy-Constrained Microprocessor Pipeline Design

Flip-flops are basic sequential elements in digital circuits and they have a deep impact on the performance of the circuits. In order to reduce the redundant transitions at internal nodes of the flip-flop, a conditional clock technique is proposed, and then a conditional clock pulse-triggered flip-flop (CCFF) based on this technique is designed. In CCFF, the clock is blocked when the input remains unchanged so that the internal nodes will not switch with the clock, which reduces the power consumption effectively. Based on the TSMC 0.18μm technology, the post-layout simulation results show that the proposed CCFF has an obvious advantage in power consumption when the data switching activity factor is below 50% as compared with other state-of-the-art pulse-triggered flip-flops, and the power saving is more than 50% when the activity factor is 10%.

Design of a low-power pulse-triggered flip-flop with conditional clock technique

Low-power level converting flip-flop with a conditional clock technique in dual supply systems

Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.

Liang Geng

Papers

Design of a low-power pulse-triggered flip-flop with conditional clock technique

Low-power level converting flip-flop with a conditional clock technique in dual supply systems

Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique