Showing papers in "Journal of Circuits, Systems, and Computers in 2015"

Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations

Abstract: In this paper, we propose two novel soft error tolerant latch circuits namely HRPU and HRUT. The proposed latches are both capable of fully tolerating single event upsets (SEUs). Also, they have the ability of enduring single event multiple upsets (SEMUs). Our simulation results show that, both of our HRPU and HRUT latches have higher robustness against SEMUs as compared with other recently proposed radiation hardened latches. We have also explored the effects of process and temperature variations on different design parameters such as delay and power consumption of our proposed latches and other leading SEU tolerant latches. Our simulation results also show that, compared with the reference (unprotected) latch, our HRPU latch has 57% and 34% improvements in propagation delay and power delay product (PDP) respectively. In addition, process and temperature variations have least effects on HRPU in comparison with the other latches. Allowing little more delay, we designed HRUT latch that can filter single event transients (SETs). HRUT has been designed to be immune against SEUs, SEMUs and SETs with an acceptable overhead and sensitivity to process and temperature variations.

High Performance Voltage-Mode Tunable All-Pass Section

Abstract: This paper presents a voltage-mode (VM) tunable all-pass section, employing a grounded capacitor and a newly introduced current conveyor with an extra X stage. The proposed all-pass filter uses grounded capacitor as the only passive component and benefits from high input and low output impedance. The proposed circuit exhibits eight performance features without trade-offs, as compared to carefully chosen 25 published works. The functionality of the proposed element is verified through PSPICE simulation using 0.25-μm process parameters. An application of second order is also incorporated.

Midpoint Memory: A Special Memory Structure for Data-Oriented Models Implementation

Abstract: Introducing data-oriented theory in recent years and its successful applications in engineering and applied science and by requirements to new memory structure for managing data efficiently, lead us to present a new memory module for implementation of data-oriented models. Most of concepts in data-oriented theory are modeled as problem-solution data structure. In this paper for suitable management these kinds of data structures, a special content addressable memory with fast access is designed which is named Midpoint memory.

Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops

Abstract: Quantum-dot Cellular Automata (QCA) is an attractive nanoelectronics paradigm which is widely advocated as a possible replacement of conventional CMOS technology. Designing memory cells is a very i...

Sub-Volt Fully Balanced Differential Difference Amplifier

Abstract: This paper presents a new CMOS structure for a fully balanced differential difference amplifier (FB-DDA) designed to operate from a sub-volt supply. This structure employs the bulk-driven quasi-floating-gate (BD-QFG) technique to achieve the capability of an ultra-low voltage operation and an extended input voltage range. The proposed BD-QFG FB-DDA is suitable for ultra-low-voltage low-power applications. The circuit is designed with a single supply of 0.5 V and consumes only 357 nW of power. The proposed circuit was simulated in a 0.18-μm TSMC CMOS technology and the simulation results prove its functionality and attractive parameters. An application example of a state variable filter is also presented to confirm the usefulness of the proposed BD-QFG FB-DDA.

Design of a Variable Fractional Delay Filter Using Comprehensive Least Square Method Encompassing All Delay Values

Abstract: The work presented in this paper is concerned with the designing of a variable fractional delay (VFD) FIR filter using least square method encompassing all delay values p. First, the frequency response, e-jωp, of the VFD filter is approximated using power series expansion of an exponential function and then, it is represented in terms of frequency response of the differentiator. Next, the proposed least square method adopts a novel cost function which includes all the fractional delay values. Finally, design and application examples are given to illustrate that the proposed least square method have better design accuracy and significantly reduction in magnitude error with the same degree of complexity than existing least square methods.

Fractional-Order 2 × n RLC Circuit Network

Abstract: This paper introduces new fundamentals of the 2 × n RLC circuit network in the fractional-order domain. First, we derive the three general formulae of the equivalent impedances of the circuit network by using the matrix transform methods and constructing the differential equation models in three different cases. Moreover, we systematically study the effects of the system parameters on the impedence characteristics in the three different cases. Specifically, the new phenomena and laws are presented by the results of the numerical simulations, which are impossible in the conventional cases. Finally, a comparative sensitivity analysis about the three cases with respect to the fractional orders for the fractional-order circuit network is carried out in detail. Mathematical analyses and numerical simulations are included to validate the study.

Crosstalk Induced Delay Analysis of Randomly Distributed Mixed CNT Bundle Interconnect

Abstract: In this paper, a more realistic analytical model for randomly distributed mixed carbon nanotube (CNT) bundle (MCB) is presented for the analysis of crosstalk induced delay. Several researchers have proposed analytical models for interconnects based on single-walled CNT (SWCNT), multi-walled CNT (MWCNT) bundle and most interestingly, spatially arranged mixed CNTs. Although, bundled SWCNTs and MWCNTs are easily realizable, but, practically it is almost impossible to fabricate a MCB with precise arrangements of SWCNTs and MWCNTs. Motivated by these facts, this paper presents a corner placement algorithm for randomly distributed SWCNTs and MWCNTs of different diameters in a MCB. The performance of MCB is compared with that of conventional bundled SWCNT and bundled MWCNT at different coupled interconnect lengths and spacing. Encouragingly, for a fixed cross-sectional area, the overall crosstalk induced delay of MCB reduces by 65.03% and 23.54% in comparison to the bundles having either SWCNTs or MWCNTs with smaller diameters, respectively. However, in contradiction to most of the previously reported results, bundled MWCNTs with larger diameters outperform the randomly distributed MCBs in terms of crosstalk performance.

Cognitive State Estimation by Effective Feature Extraction and Proper Channel Selection of EEG Signal

Abstract: This paper presents a cognitive state estimation system focused on some effective feature extraction based on temporal and spectral analysis of electroencephalogram (EEG) signal and the proper channel selection of the BIOPAC automated EEG analysis system. In the proposed approach, different frequency components (i) real value; (ii) imaginary value; (iii) magnitude; (iv) phase angle and (v) power spectral density of the EEG data samples during different mental task performed to assess seven types of human cognitive states — relax, mental task, memory related task, motor action, pleasant, fear and enjoying music on the three channels of BIOPAC EEG data acquisition system — EEG, Alpha and Alpha RMS signal. Also the time and time-frequency-based features were extracted to compare the performance of the system. After feature extraction, the channel efficacy is evaluated by support vector machine (SVM) based on the classification rate in different cognitive states. From the experimental results and classification accuracy, it is determined that the overall accuracy for alpha channel shows much improved result for power spectral density than the other frequency based features and other channels. The classification rate is 69.17% for alpha channel whereas for EEG and alpha RMS channel it is found 47.22% and 32.21%, respectively. For statistical analysis standard deviation shows better result for alpha channel and it is found 65.4%. The time-frequency analysis shows much improved result for alpha channel also. For the mean value of DWT coefficients the accuracy is highest and it is 81.3%. Besides the classification accuracy, SVM shows better performance in compare with kNN classifier.

A Routing Aggregation for Load Balancing Network-on-Chip

Abstract: A routing aggregation (RA) is proposed for load balancing network-on-chip (NoC). The computing nodes with dense traffic and long distance in network are gathered into the same routing node to form a super router. A load balancing routing algorithm for super router is presented to improve the overall performance of NoC. A simulation platform using System C is presented to confirm the feasibility of the proposed design in 2D mesh. The simulation results show that the proposed RA design can reduce the average packet latency and the standard deviation of host link utilization 8% and 33%, respectively compared with the reported routing methods. The area cost and power consumption compared with the reported schemes are 22% and 12% less, respectively.

Robust Pornography Classification Solving the Image Size Variation Problem Based on Multi-Agent Learning

Abstract: This study proposed a pornography classifier using multi-agent learning as a combination of the Bayesian method using color features extracted from skin detection based on the YCbCr color space and the back-propagation neural network method using shape features also extracted from skin detection. The classification of pornographic images was made more robust to the variation of images despite size engineering problems. Previous studies failed to achieve such robustness. Findings showed that the proposed multi-agent learning-based pornography classifier has produced significant TP and TN average rates (i.e., 96% and 97.33%, respectively). In addition, the proposed classifier has achieved a significantly low average rate of FN and FP (i.e., only 4% and 2.67%, respectively). The implementation of this algorithm is crucial and significant not only in identifying pornography but also in blocking Web sites that covertly promote pornography.

Reconfigurable Hardware for Machine Learning Applications

Abstract: This paper proposes universal coarse-grained reconfigurable computing architecture for hardware implementation of decision trees (DTs), artificial neural networks (ANNs), and support vector machines (SVMs), suitable for both field programmable gate arrays (FPGA) and application specific integrated circuits (ASICs) implementation. Using this universal architecture, two versions of DTs (functional DT and axis-parallel DT), two versions of SVMs (with polynomial and radial kernel) and two versions of ANNs (multi layer perceptron ANN and radial basis ANN) machine learning classifiers, have been implemented in FPGA. Experimental results, based on 18 benchmark datasets of standard UCI machine learning repository database, show that FPGA implementation provides significant improvement (1–2 orders of magnitude) in the average instance classification time, in comparison with software implementations based on R project.

Design of a 10-Bit High Performance Current-Steering DAC with a Novel Nested Decoder Based on Domino Logic

Abstract: In this paper, a 10-bit 8-2 segmented current-steering digital-to-analog converter (DAC) is presented which uses a novel nested binary to thermometer (BT) decoder based on domino logic gates. High accuracy and high performances are achieved with this structure. The proposed decoder has a pipelining scheme and it is designed symmetrically in three stages with repeatable logic gates. Thus, power consumption, chip area and the number of control signals are reduced. The proposed DAC is simulated in 0.18-μm CMOS technology and the spurious-free dynamic range (SFDR) is 65.3 dB over a 500 MHz output bandwidth at 1 GS/s. Total power consumption of the designed DAC is only 23.4 mW while the digital and analog supply voltages are 1.2 and 1.8 V, respectively. The active area of the proposed DAC is equal to 0.3 mm2.

High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation

Abstract: By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB open-loop DC gain, 20 MHz UGF and 145 dB CMRR @ 1.2 V supply voltage while the power consumption is 400 μW which makes it suitable for low-voltage applications.

Architecture and Network-on-Chip Implementation of a New Hierarchical Interconnection Network

Abstract: A Midimew-connected Mesh Network (MMN) is a minimal distance mesh with wrap-around links network of multiple basic modules (BMs), in which the BMs are 2D-mesh networks that are hierarchically interconnected for higher-level networks. In this paper, we present the architecture of the MMN, addressing of node, routing of message, and evaluate the static network performance of MMN, TESH, mesh and torus networks. In addition, we propose the network-on-chip (NoC) implementation of MMN. With innovative combination of diagonal and hierarchical structure, the MMN possesses several attractive features, including constant degree, small diameter, low cost, small average distance, moderate bisection width and high fault tolerant performance than that of other conventional and hierarchical interconnection networks. The simple architecture of MMN is also highly suitable for NoC implementation. To implement all the links of level-3 MMN, only four layers are needed which is feasible with current and future VLSI technologies.

A 80-MHz-to-410-MHz 16-Phases DLL Based on Improved Dead-Zone Open-Loop Phase Detector and Reduced-Gain Charge Pump

Abstract: In this paper, a low jitter 16-phases delay locked loop (DLL) is proposed based on a simple and sensitive phase detector (PD). Dead-zone of the proposed PD is improved in compare to the conventional structures where the pulse generator postpones PD response and reduces the sensitivity. Also, the conventional structure of charge pumps is modified to inject small charge throughout the continuous outputs of PD. Smaller bias current is provided in charge pump via subtracting tail currents of intentionally mismatched differential pairs. Duty cycle of output differential phases is adjusted to around 50% using common mode setting strategy on delay elements. Simulation results confirm that DLL loop can provide 16-phases in frequency range of 80 to 410 MHz, consuming total power of 3.5 and 5.6 mW, respectively. The dead-zone of PD is also reduced from 80 to 14 ps when the pulse generator section is eliminated. Also, RMS jitter of about 45 and 1.76 ps are obtained at 80 and 410 MHz, respectively, when the supply voltage is subject to around 40 mV peak-to-peak noise disturbances. The proposed DLL can be implemented in less than 0.05 mm2 active area in a 0.18 μm CMOS technology.

Automatic Simplified Symbolic Analysis of Analog Circuits Using Modified Nodal Analysis and Genetic Algorithm

Abstract: In this paper, a hybrid methodology based on modified nodal analysis (MNA) and genetic algorithm (GA) is presented for simplified symbolic small-signal analysis of analog circuits containing semiconductor devices like MOSFETs. At first, the circuit is analyzed by the MNA, and the derived exact continuous-time transfer function is automatically simplified via GA. We propose a new multi-objective criterion for symbolic simplification of continuous-time transfer functions, which can be performed by such optimization algorithms as local-search algorithms, heuristic algorithms, swarm-intelligence algorithms, etc. In this paper, GA is used to validate the proposed simplification criterion. All processes including netlist text pre-processing, symbolic analysis via MNA, post-processing, and simplification via GA are consecutively run in an m-file MATLAB program. The comparison of obtained numeric results with HSPICE demonstrates the efficiency of the proposed methodology.

An Adaptive Neuro-Fuzzy Model to Multilevel Inverter for Grid Connected Photovoltaic System

Abstract: This paper proposed an adaptive neuro-fuzzy model (ANFIS) to multilevel inverter (MLI) for grid connected photovoltaic (PV) system. The purpose of the proposed controller is that it is not requiring any optimal pulse width modulated (PWM) switching-angle generator and proportional–integral controller. The proposed method strictly prohibits the variations present in the output voltage of the cascaded H-bridge MLI. In this method, the ANFIS have the input which is grid voltage, the difference voltage and the output target is control voltage. By using these parameters, the ANFIS makes the rules and has been tuned perfectly. During the testing time, the ANFIS gives the control voltage according to the different inputs. The resultant control voltage equivalent gate pulses are utilized for controlling the insulated gate bi-polar switches (IGBT) of MLI. Then the ANFIS based MLI for grid connected PV system is implemented in the MATLAB/simulink platform and the effectiveness of the proposed control technique is a...

A Synthesis Method of Quantum Reversible Logic Circuit Based on Elementary Qutrit Quantum Logic Gates

Abstract: Because ternary computer has more superiority than other d-ary number systems, we focus on the investigation of ternary elementary quantum gates and the synthesis algorithm of ternary quantum logic circuits. Above all, Pauli operators and their matrices on qutrit are introduced. Then eight qutrit operators are selected as elementary operators and eight qutrit quantum logic gates are defined. Permutation groups are introduced to characterize the quantum gates and quantum logic circuits. Some important qutrit quantum logic gates are defined also, such as QNOT, QKCXi, EQKCXi, QSwap, QCNOT and EQCNOT. Based on these elementary gates, we prove two very important theorems: (1) all qutrit quantum reversible logic circuit can be generated by Xi gate and QKCXi gate; (2) all qutrit quantum reversible logic circuits can be generated by Xi gate and QCNOT gate. The two theorems indicate that any complicated qutrit quantum reversible circuit can be constructed by the simplest ternary quantum gate. This will greatly simplify the implementation difficulty of quantum circuit. Subsequently, we propose a synthesis algorithm for qutrit quantum reversible logic circuit, which is verified through simulation experiment by the computer program we have designed.

A Game Theory-Based Heuristic for the Two-Dimensional VLSI Global Routing Problem

Abstract: In this work we propose a game theory (GT)-based global router. It works in two steps: (i) Initial routing of all nets using maze routing with framing (MRF) and (ii) GT-based rip-up and reroute (R&R) process. In initial routing, the nets are divided into several small subsets which are routed concurrently using multithreading (MT). The main task of the GT-based R&R process is to eliminate congestion. Nets are considered as players and each player employs two pure strategies: (attempt to improve its spanning tree, and, do not attempt to improve its spanning tree). The nets also have mixed strategies whose values act as probabilities for them to select any particular pure strategy. The nets which select their first strategy will go through the R&R operation. We also propose an algorithm which computes the mixed strategies of nets. The advantage of using GT to select nets is that it reduces the number of nets and the number of iterations in the R&R process. The performance of the proposed global router was evaluated on ISPD'98 benchmarks and compared with two recent global routers, namely, Box Router 2.0 (configured for speed) and Side-winder. The results show that the proposed global router with MT has a shorter runtime to converge to a valid solution than that of Box Router 2.0. It also outperforms Side-winder in terms of routability. The experimental results demonstrated that GT is a valuable technique in reducing the runtime of global routers.

Analysis of Phase Noise in 28 nm CMOS LC Oscillator Differential Topologies: Armstrong, Colpitts, Hartley and Common-Source Cross-Coupled Pair

Abstract: Comparative Phase Noise analyses of common-source cross-coupled pair, Colpitts, Hartley and Armstrong differential oscillator circuit topologies, designed in 28 nm bulk CMOS technology in a set of common conditions for operating frequencies in the range from 1 GHz to 100 GHz, are carried out in order to identify their relative performance. The impulse sensitivity function (ISF) is used to carry out qualitative and quantitative analyses of the noise contributions exhibited by each circuit component in each topology, allowing an understanding of their impact on phase noise. The comparative analyses show the existence of five distinct frequency regions in which the four topologies rank unevenly in terms of best phase noise performance. Moreover, the results obtained from the ISF show the impact of flicker noise contribution as the major effect leading to phase noise degradation in nanoscale CMOS LC oscillators.

A Wide-Range Low-Jitter PLL Based on Fast-Response VCO and Simplified Straightforward Methodology of Loop Stabilization in Integer-N PLLs

Abstract: A straightforward methodology of optimizing ring-oscillator phase-locked loops (PLLs) is organized for integer-N PLLs. Then, a brief 4-step design flow is concluded to implicitly quantize the loop components for optimized loop stability. Theoretical analysis confirms that the ratio of more than 20 is required for loop filter's capacitors to yield at least 65° degrees phase margin. A wide-range voltage controlled oscillator (VCO) is proposed which is continuously controlled through two fast and slow response paths. The fast-response path improves RMS jitter due to decreasing loop delay and the slower one is an adaptive bias tuning loop, utilized to reduce the power consumption at lower operating frequencies. The RMS jitter of around 2 ps and 0.35 ps at 250 MHz and 4 GHz operating frequencies are obtained, respectively, where the 1.8 V supply voltage is subjected to about 60 mV peak-to-peak noise and reference clock suffers from 12 ps peak-to-peak jitter. Power consumption is reduced from 12.6–4 mW at 250 MHz operating frequency when the adaptive bias scheme is applied. Furthermore, simulation results confirm 35% and 50% improvement in RMS and peak-to-peak jitter at 250 MHz operating frequency, respectively, when the ratio of capacitances is increased from 10 to 20 within the loop filter. The proposed PLL can be implemented in 170 μm × 250 μm active area in 0.18 μm CMOS process.

Investigation of the Half Bridge and Transformer Push–Pull Pulser Topologies for Ultrasonic Transducer Excitation

Abstract: Comparison of two high power pulser topologies is presented. Pulser design was aimed for piezoelectric transducer excitation, yet it can also be used for electromagnetic acoustic transducer (EMAT) or capacitive micromachined ultrasonic transducers (CMUTs) excitation. Pulser can produce both single rectangular pulse and trains of rectangular arbitrary duration pulses. In order to achieve the economy of the electrical power consumption and speed both high-pulling and low-pulling elements are active switches. Energy per pulse was used to evaluate the amount of energy consumed. Two topologies were selected for evaluation: transformer output push–pull topology and half bridge output. Experimental investigation results are presented.

High-Speed, High-Frequency and Low-PDP, CNFET Full Adder Cells

Abstract: In this paper, three CNT-based full adder designs, called Design1, Design2 and Design3, are proposed. In these designs 12, 14 and 16 transistors are used, respectively. In all designs only 3-input NAND, Majority-not and NOR functions are used. First, a preliminary structure (Design1) is presented using 12 transistors. Then its weaknesses are tackled in two steps. In fact, in each step a new design is presented by adding two more transistors to its predecessor. Therefore two new structures called Design2 and Design3 are built in which Design3 is the most efficient one. To study the performance of Design3 versus other silicon-based and CNT-based 32-nm classical and state-of-the-art cells, comprehensive simulations with regard to various supplies, loads, operating frequencies, and temperatures are performed using Synopsys HSPICE tool. Simulation results confirm that the proposed cell is superior to the other cells. At last the robustness of Design3 against the diameter mismatches of CNTs which is one of the ...

A Constructive Heuristic for Application Mapping onto Mesh Based Network-on-Chip

Abstract: Mapping constitutes a very important step in network-on-chip (NoC)-based implementation of an application. An application is often represented in the form of an application core graph. The cores of the core graph communicate between themselves using the underlying network. This paper presents a constructive heuristic to statically map applications on two-dimensional mesh-connected NoC. The approach corresponds to a design time decision of attachment of cores to the routers. The mapping results, in terms of overall communication cost metric, have been compared with many well-known techniques reported in the literature and also with an exact method built around integer linear programming (ILP). A thorough complexity analysis of the algorithm has been performed. For smaller benchmarks, the results obtained are same as those for the ILP generated solutions. For benchmarks containing 64 and higher number of cores, the mapping solutions are better than the existing ones. Dynamic performances of the mapped solutions have been compared with respect to synthetically generated self-similar traffic. In many cases, our approach requires less latency and energy per packet than the existing methods while providing higher throughput.

An FPGA Architecture for the Recovery of WPA/WPA2 Keys

Abstract: Wi-Fi protected access (WPA) has provided serious improvements over the now deprecated wired equivalent privacy (WEP) protocol. WPA, however, still has some flaws that allow an attacker to obtain the passphrase. One of these flaws is exposed when the access point (AP) is operating in the WPA personal mode. This is the most common mode, as it is the quickest and easiest to configure. This vulnerability requires the attacker to capture the traffic from the four-way handshake between the AP and client, and then have enough compute time to reverse the passphrase. Increasing the rate at which passphrases can be reversed reduces the amount of time required to construct a repository of service set identifiers (SSIDs) and passphrases, which can increase the chances an attack is successful, or, alternatively, reduce the difficulty of auditing a wireless network for security purposes. This work focuses on creating an field programmable gate array (FPGA)-based architecture to accelerate the generation of a WPA/WPA2 pairwise master key (PMK) lookup table (LUT) for the recovery of the passphrase, with special emphasis on the secure hash algorithm-1 (SHA-1) implementation. PMK generation relies heavily on SHA-1 hashing and, as this work shows, an optimized SHA-1 implementation can achieve up to a 40 × speedup over an unoptimized implementation when generating PMKs.

An 8-Bit 0.333–2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS

Abstract: This paper presents an 8-bit configurable time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). By using a mode selection circuit, four modes of sampling rate are provided: Single channel at 333.3 MS/s, 2-channel at 666.7 MS/s, 3-channel at 1 GS/s and 6-channel at 2 GS/s. An on-chip delay-locked loop (DLL) uniformly generates six-phase clock with 20% duty cycle, and the timing errors are reduced to a tolerable range. In low sampling rate modes, the corresponding sampling switches and comparators in the idle sub-ADCs are shut down to save power consumption. Based on the 65-nm CMOS technology, the post-layout simulation results show that at 1.2 V supply, the proposed ADC consumes 8.6, 10.9, 13.1 and 19.9 mW under different modes. With an ENOB of 7.92, 7.34, 7.01 and 6.37 bit, this results in a FOM of 106.6, 100.9, 101.6 and 120.3 fJ/conversion-step respectively.

A New Class of Chaotic Circuit with Logic Elements

Abstract: When signum operation is applied in chaotic systems to realize piecewise-linearity, the original nonlinearity turns to be a kind of Boolean calculation, and correspondingly the chaotic circuit can be implemented by an analog structure embedded with some logic-gate circuits. In this paper, as examples based on the diffusionless Lorenz system we proposed a couple of chaotic flows with signum piecewise-linearity, which experimentally resorts to digital gate circuits. The experimental chaotic circuit with logic elements was built, and the oscillation in the physical circuit agrees well with the numerical simulation.

Using Cascaded Non-Identical CIC Sections to Improve Insertion Loss

Abstract: A novel class of cascaded-integrator-comb (CIC) filter functions, which preserve the CIC filter simplicity avoiding the multipliers, is proposed in this paper. The proposed class is designed using several cascaded non-identical CIC sections. The paper provides its non-recursive and recursive forms, as well as frequency response. Compared with classical CIC finite impulse response (FIR) filters designed novel class shows excellent performances in term of insertion loss in stopband and selectivity. To verify the behavior of the proposed novel class of CIC FIR filter functions, several illustrative examples are provided. Also, comparisons of the novel filter class with existing classical CIC structures and some recent improvements given in the literature are provided. For the same level of a constant group delay of 31.5 s, a classical CIC filter function has insertion loss of 115.176 dB, and proposed novel filter function has 136.757 dB. It has achieved significant improvement of 21.581 dB or approximately about 20%.

High-Speed and Area-Efficient Reconfigurable Multiplexer Bank for RAM-Based Finite State Machine Implementations

Abstract: This work is focused on the problem of designing efficient reconfigurable multiplexer banks for RAM-based implementations of reconfigurable state machines. We propose a new architecture (called combination-based reconfigurable multiplexer bank, CRMUX) that use multiplexers simpler than that of the state-of-the-art architecture (called variation-based reconfigurable multiplexer bank, VRMUX). The performance (in terms of speed, area and reconfiguration cost) of both architectures is compared. Experimental results from MCNC finite state machine (FSM) benchmarks show that CRMUX is faster and more area-efficient than VRMUX. The reconfiguration cost of both multiplexer banks is studied using a behavioral model of a reconfigurable state machine. The results show that the reconfiguration cost of CRMUX is lower than that of VRMUX in most cases.