The invention relates to an analog front end circuit applied for EEG signal acquiring. The analog front end circuit comprises an input-feedback chopped wave module, a capacitance coupling module, twochannel amplifier modules and a resistance partial voltage module, wherein the input-feedback chopped wave module is provided with two EEG signal ends for receiving the input of two paths of the EEG signals, performing frequency modulation on the EEG signals, and outputting the EEG signals after frequency modulation to the capacitance coupling module; the capacitance coupling module is used for performing coupling treatment on the EEG signals after frequency modulation and outputting the EEG signals after coupling treatment to the two channel amplifier modules; the two channel amplifier modules are used for amplifying the EEG signals after coupling treatment and outputting the amplified EEG signals to the resistance partial voltage module; and the resistance partial voltage module is usedfor performing voltage partial treatment of the amplified EEG signals and outputting the amplified EEG signals to the feedback end of the input-feedback chopped wave module. According to the analog front end circuit disclosed by the invention, input impedance is increased, attenuation of the amplitude of the EEG signals is reduced, the EEG signals can be completely obtained, and the acquiring accuracy of the EEG signals is improved.

Analog front end circuit applied for EEG signal acquiring

The present invention provides a circuit applied to a bio-information acquisition system, wherein the circuit includes a terminal, an output circuit, a feedback circuit and a calibration circuit. In the operations of the circuit, the terminal is arranged to receive an input signal, the output circuit is configured to generate an output signal according to the input signal, the feedback circuit is configured to receive the output signal to generate a current signal to the terminal, and the calibration circuit is configured to generate a control signal to control the feedback circuit to determine a level of the current signal according to the output signal.

Circuit applied to bio-information acquisition system

This paper presents a novel digitally-controlled DC offset calibration (DCOC) circuit for the chopper instrumentation amplifiers that offers better robustness, faster calibration speed, and lower average input noise than traditional integrator-based structures. Different from the traditional analog method, the proposed structure adopts digital circuit to cancel most of the offset introduced by the input-electrode, and the residual offset is eliminated by the second-stage capacitive-coupling amplifier. The difference of two reference voltages is used as the loop-output calibration voltage, so that the system has good temperature characteristic and process characteristic. The noise introduced by the digital offset calibration loop is proportional to the magnitude of the input offset, and no noise is introduced when the input offset is 0V. The circuit is designed in 0.18μm standard CMOS process with the supply voltage of 1.2V. The total power consumption is 36μW and the instrumentation amplifier consumes 7μW. The simulation results demonstrate the effectiveness of the amplifier functionality under different offset voltages, which can eliminate the offset up to ±300mV. Under different offset voltages, the input integrated noise range is 0.67~ 1.49μVrms (0.1~150Hz).

A Novel Digitally-Controlled DC Offset Calibration Circuit for the Chopper Instrumentation Amplifier

In this paper, a new approach is proposed for designing ultra-low-power FFT (Fast Fourier Transform) system suitable for use in energy harvesting powered sensors. Bit-serial architecture is adopted to reduce the power consumption of butterfly operation. Simulation results show that, compared with state-of-the-art bit-serial and conventional parallel FFT processors, the proposed technique is superior in terms of silicon area, power consumption, dynamic energy use due to variable precision arithmetic. A sample design of a 64-point FFT shows that the implementation can save about 40% area and 36% leakage power compared with a conventional parallel counterpart, accordingly achieving significant power benefits at a low sample rate and low voltage domain. The dynamic variation of the arithmetic precision can be achieved through a simple modification of the controller with hardware area overhead of 10% gate count.

Lianxi Liu

Papers

A Novel Digitally-Controlled DC Offset Calibration Circuit for the Chopper Instrumentation Amplifier

A Bit-Serial Variable-Accuracy FFT Processor For Energy-Harvesting Systems