[신간의 별자리x] 우리/미술, 그리고 ‘슬픔의 박물관’

a 'sleeper', receiving only modest attention for 50 years before emerging as a cornerstone of communications engineering in more recent times. Roughly one in six of Walsh's 281 publications are included, photographically reproduced. Reproduction is excellent except for one paper from 1918. The book also reproduces three brief papers about Walsh and his work, by W. E. Sewell, D. V. Widder and Morris Marden. The first two were written for a special issue of the SIAM Journal celebrating Walsh's 70th birthday; the third is an obituary.

Matrix iterative analysis (2nd edn), by Richard S. Varga. Springer Series in Computational Mathematics 27. Pp. 358. £55. 2000. ISBN 3 540 66321 5 (Springer Verlag).

Preparing the books to read every day is enjoyable for many people. However, there are still many people who also don't like reading. This is a problem. But, when you can support others to start reading, it will be better. One of the books that can be recommended for new readers is computer aided analysis of electronic circuits algorithms and computational techniques. This book is not kind of difficult book to read. It can be read and understand by the new readers.

Computer-aided analysis of electronic circuits: Algorithms and computational techniques

Supercapacitors (SCs) have high power density and exceptional durability. Progress has been made in their materials and chemistries, while extensive research has been carried out to address challenges of SC management. The potential engineering applications of SCs are being continually explored. This paper presents a review of SC modeling, state estimation, and industrial applications reported in the literature, with the overarching goal to summarize recent research progress and stimulate innovative thoughts for SC control/management. For SC modeling, the state-of-the-art models for electrical, self-discharge, and thermal behaviors are systematically reviewed, where electrochemical, equivalent circuit, intelligent, and fractional-order models for electrical behavior simulation are highlighted. For SC state estimation, methods for State-of-Charge (SOC) estimation and State-of-Health (SOH) monitoring are covered, together with an underlying analysis of aging mechanism and its influencing factors. Finally, a wide range of potential SC applications is summarized. Particularly, co-working with high energy-density devices constitutes hybrid energy storage for renewable energy systems and electric vehicles (EVs), sufficiently reaping synergistic benefits of multiple energy-storage units.

A review of supercapacitor modeling, estimation, and applications: A control/management perspective

This paper presents a low power boost converter for thermoelectric energy harvesting that demonstrates an efficiency that is 15% higher than the state-of-the-art for voltage conversion ratios above 20. This is achieved by utilizing a technique allowing synchronous rectification in the discontinuous conduction mode. A low-power method for input voltage monitoring is presented. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. The converter, fabricated in a 0.13 μm CMOS process, operates from input voltages ranging from 20 mV to 250 mV while supplying a regulated 1 V output. The converter consumes 1.6 (1.1) μW of quiescent power, delivers up to 25 (175) μW of output power, and is 46 (75)% efficient for a 20 mV and 100 mV input, respectively.

A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting

Supercapacitors are often used in energy harvesting wireless sensor nodes (EH-WSNs) to store harvested energy. Until now, research into the use of supercapacitors in EH-WSNs has considered them to be ideal or oversimplified, with non-ideal behavior attributed to substantial leakage currents. In this brief, we show that observations previously attributed to leakage are predominantly due to redistribution of charge inside the supercapacitor. We confirm this hypothesis through the development of a circuit-based model, which accurately represents non-ideal behavior. The model correlates well with practical validations representing the operation of an EH-WSN and allows behavior to be simulated over long periods.

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Accurate Supercapacitor Modeling for Energy Harvesting Wireless Sensor Nodes

This paper presents an efficient carbon nanotube (CNT) transistor modeling technique that is based on cubic spline approximation of the nonequilibrium mobile charge density. The approximation facilitates the solution of the self-consistent voltage equation in a CNT so that calculation of the CNT drain-source current is accelerated by at least two orders of magnitude. A salient feature of the proposed technique is its ability to incorporate both ballistic and nonballistic transport effects without a significant computational cost. The proposed models have been extensively validated against reported CNT ballistic and nonballistic transport theories and experimental results.

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Numerically Efficient Modeling of CNT Transistors With Ballistic and Nonballistic Effects for Circuit Simulation

A tutorially orientated account of the principles underlying circuit level simulation forms the basis for discussing reliability of circuit level simulation. An outline of equation formulation and time discretisation of the equations is followed by consideration of stability of the numerical integration methods. The precision of simulation, which also depends on the integration methods used, is then discussed, with particular reference to the analysis parameters of the SPICE simulator. A descriptive account of the Newton-Raphson method of solving the nonlinear algebraic equations, derived from the discretised differential equations, is then presented again with relation to SPICE parameters. The reasons for convergence failure in both transient and DC simulation are related to the underlying principles of simulation and possible ill conditioning of the circuit. The paper includes some simple simulation examples of problematic situations.

Overview of SPICE-like circuit simulation algorithms

Flip-flops (FFs) are essential building blocks of sequential digital circuits but typically occupy a substantial proportion of chip area and consume significant amounts of power. This paper proposes 18-transistor single-phase clocked (18TSPC), a new topology of fully static contention-free single-phase clocked (SPC) FF with only 18 transistors, the lowest number reported for this type. Implemented in 65-nm CMOS, it achieves 20% cell area reduction compared to the conventional transmission gate FF (TGFF). Simulation results show the proposed 18TSPC is two times more efficient than TGFF in the energy-delay space. To demonstrate EDA compatibility and circuit/system-level benefits, a shift register and an AES-128 encryption engine have been implemented. Chip experimental measurements at 0.6 V, 25 °C show that, compared to TGFF, the proposed 18TSPC achieves reductions of 68% and 73% in overall and clock dynamic power, respectively, and 27% lower leakage.

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Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

This paper presents a SPICE compatible model of a dual-gate bilayer graphene field-effect transistor. The model describes the functionality of the transistor in all the regions of operation for both hole and electron conduction. We present closed-form analytical equations that define the boundary points between the regions to ensure Jacobian continuity for efficient circuit simulator implementation. A saturation displacement current is proposed to model the drain current when the channel becomes ambipolar. The model proposes a quantum capacitance that varies with the surface potential. The model has been implemented in Berkeley SPICE-3, and it shows a good agreement against experimental data with the normalized root-mean-square error less than $10\%$ .

Tom J. Kazmierski

Papers

Accurate Supercapacitor Modeling for Energy Harvesting Wireless Sensor Nodes

Numerically Efficient Modeling of CNT Transistors With Ballistic and Nonballistic Effects for Circuit Simulation

Overview of SPICE-like circuit simulation algorithms

Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

A Dual-Gate Graphene FET Model for Circuit Simulation—SPICE Implementation