Multilevel inverters have created a new wave of interest in industry and research. While the classical topologies have proved to be a viable alternative in a wide range of high-power medium-voltage applications, there has been an active interest in the evolution of newer topologies. Reduction in overall part count as compared to the classical topologies has been an important objective in the recently introduced topologies. In this paper, some of the recently proposed multilevel inverter topologies with reduced power switch count are reviewed and analyzed. The paper will serve as an introduction and an update to these topologies, both in terms of the qualitative and quantitative parameters. Also, it takes into account the challenges which arise when an attempt is made to reduce the device count. Based on a detailed comparison of these topologies as presented in this paper, appropriate multilevel solution can be arrived at for a given application.

Multilevel Inverter Topologies With Reduced Device Count: A Review

With wide-spread application of power electronic systems across many different industries, their reliability is being studied extensively. This paper presents a comprehensive review of reliability assessment and improvement of power electronic systems from three levels: 1) metrics and methodologies of reliability assessment of existing system; 2) reliability improvement of existing system by means of algorithmic solutions without change of the hardware; and 3) reliability-oriented design solutions that are based on fault-tolerant operation of the overall systems. The intent of this review is to provide a clear picture of the landscape of reliability research in power electronics. The limitations of the current research have been identified and the direction for future research is suggested.

https://www.egr.msu.edu/~bingsen/files_publications/J-13_TPEL_Reliability.pdf

Survey on Reliability of Power Electronic Systems

With wide-spread application of power electronic converters in high power systems, there has been a growing interest in system reliability analysis and fault-tolerant capabilities. This paper presents a comprehensive review of conventional fault-tolerant techniques regarding power electronic converters in case of power semiconductor device failures. These techniques can be classified into four categories based on the type of hardware redundancy unit: switch-level, leg-level, module-level, and system-level. Also, various fault-tolerant methods are assessed according to cost, complexity, performance, etc. The intent of this review is to provide a detailed picture regarding the current landscape of research in power electronic fault-handling mechanisms.

Survey on Fault-Tolerant Techniques for Power Electronic Converters

Multilevel inverters (MLIs) are being used in wide range of power electronic applications. These converters have attracted a lot of attention during recent years and exist in different topologies with similar basic concepts. This paper presents five main submodules (SMs) to be used as the basic structures of MLIs. The paper reviews the common MLI topologies from the structural point of view. The topologies are divided into the different SMs to show conventional MLI configurations and future topologies that can be created from the main SMs. A comparative study between different topologies is performed in detail. The MLIs are categorized and investigated with from different perspectives such as the number of components, the ability to create inherent negative voltage, working in regeneration mode and using single dc source.

A General Review of Multilevel Inverters Based on Main Submodules: Structural Point of View

In this paper, a fault diagnostic system in a multilevel-inverter using a neural network is developed. It is difficult to diagnose a multilevel-inverter drive (MLID) system using a mathematical model because MLID systems consist of many switching devices and their system complexity has a nonlinear factor. Therefore, a neural network classification is applied to the fault diagnosis of a MLID system. Five multilayer perceptron (MLP) networks are used to identify the type and location of occurring faults from inverter output voltage measurement. The neural network design process is clearly described. The classification performance of the proposed network between normal and abnormal condition is about 90%, and the classification performance among fault features is about 85%. Thus, by utilizing the proposed neural network fault diagnostic system, a better understanding about fault behaviors, diagnostics, and detections of a multilevel inverter drive system can be accomplished. The results of this analysis are identified in percentage tabular form of faults and switch locations

Fault Diagnostic System for a Multilevel Inverter Using a Neural Network

A new topology with fault-tolerant ability that improves the reliability of multilevel converters is proposed. This new topology is developed through analysis of different power device's failure modes. With the proposed scheme, the function of the power stage can be maintained even part of it fails. Its fault-tolerant ability results from the redundant nature of the multiswitching-state topology and from control signal modification. Furthermore, it balances the voltage levels automatically without any assistance from other circuits. The validity of the proposed scheme is confirmed by experiments in a five-level single-phase inverter prototype.

A multilevel converter topology with fault-tolerant ability

A new topology with fault tolerant ability is proposed to improve the reliability of multilevel converters, which is based on the analysis of different power devices failure modes. With the proposed scheme, the function of the power stage can be maintained even part of it fails. The fault tolerant ability is resulted from the inherent redundant nature of the multiswitching-states topology and control signals modification. Further more, the topology balances the voltage levels automatically except for achieving fault-tolerance. The validity of the proposed scheme is confirmed by experiments in a five-level inverter prototype.

Lifeng Chen

Papers

A multilevel converter topology with fault-tolerant ability

A multilevel converter topology with fault tolerant ability