FFT implementation with fused floating-point operations

The floating point processor is the backbone of digital signal processing units In real time applications it is necessary to have a powerful processor which has a very high level of precision This can only be achieved using a floating point unitWe are going to incorporate various instructions which will be serving for a dynamic range of applications The floating point unit needs to be fast enough to process real time signals An efficient design of the floating point processor can help in reducing the area and increasing the speed

Design and implementation of floating point processor

The Java programming language provides binary floating-point primitive data types such as float and double to represent decimal numbers. However, these data types cannot represent decimal numbers with complete accuracy, which may cause precision errors while performing calculations. To achieve better precision, Java provides the BigDecimal class. Unlike float and double, which use approximation, this class is able to represent the exact value of a decimal number. However, it comes with a drawback: BigDecimal is treated as an object and requires additional CPU and memory usage to operate with. In this paper, statistical data are presented of performance impact on using BigDecimal compared to the double data type. As test cases, common mathematical processes were used, such as calculating mean value, sorting, and multiplying matrices.

Performance Analysis of BigDecimal Arithmetic Operation in Java

Math coprocessors are vital components in modern computing to improve the overall performance of the system. The AMIR CPU is a homegrown softcore 32-bit CPU that can only handle integer numbers making it inadequate for high-performance real-time systems. The aim of this project is to design and develop a math coprocessor for the AMIR CPU that can perform addition, subtraction, multiplication and division on IEEE-754 single precision floating-point numbers. The design of the math coprocessor is devised and improved based on past works on IEEE 754 floating-point operations and math coprocessor implementations. The architecture of the proposed math coprocessor consists of a control unit with instruction decode, floating-point computation unit and a register file. The architecture type is a serial controller with pipelined data path. The proposed math coprocessor retrieves instruction from the instruction register, decodes it, retrieves operands from the CPU register, performs computation then stores the results into the internal register, pending retrieval from the AMIR CPU. The proposed math coprocessor managed to achieve at least 99.999% accuracy for all four arithmetic operations with a maximum frequency of 63.8 MHz, while utilizing less than 30% of the available resource on board an Intel Cyclone IV EP4CE10E22C8 FPGA. The design is not without flaws as the proposed design has problems with instruction queueing due to the absence of an instruction buffer. Nevertheless, with further improvements and features, the proposed math coprocessor has the potential to enable the AMIR CPU to be used in a wide range of applications.

FPGA-based design of a math co-processor for the Amir CPU

The paper focuses on extending the checkability of LUT-oriented circuits for FPGA-based (Field Programmable Gate Array) digital components. The main provisions of the article concentrate on the task of ensuring the checkability for critical computer systems. As critical systems, the article considers computer systems that control high-risk facilities or ensure the functional safety of such facilities. Traditionally, approaches that are based on fault tolerance have been used to ensure the functional safety of computer systems. The specific of critical systems is that these systems must potentially operate in two modes: normal and emergency. Critical systems operate in normal mode for most of their life cycle. This mode is a long time and stable in the nature of the data processed. In this case, the input data of the system have low change activity. This leads to a decrease in the checkability of the circuits and, consequently, to the accumulation of hidden faults. When an emergency mode occurs, the activity of the input data of the system increases. The checkability of the circuit also increases. But, on the other hand, it leads to the fact that hidden faults appear. This in turn reduces the fault tolerance of the system. The paper proposes a method of checkability assessment, which analyzes faults in a circuit built on the basis of elementary LUT units. The method identifies circuit faults by faults of memory bits of LUT units. The method analyzes memory bits that are essential to the operation of the critical system in emergency mode. The complete set of memory bits is divided into two subsets: bits that are checkable in normal mode and, bits that are not checkable in this mode. The method extends the checkability of circuits by identifying the situation when the fault is caused by bits from both subsets (checkable and not checkable). Detecting this relationship of bits from different subsets gives the possibility to expand the checkability of the circuit. Experiments have been carried out to confirm the expansion of checkability for the implementation of the iterative array multiplier on FPGA.

Augmented Checkability of LUT-oriented Circuits in FPGA-based Components of Safety-Related Systems

Most of the today's processor's require fast arithmetic operation with greater accuracy and relies on floating point arithmetic for numerical calculation Addition and multiplication are the keys of floating point arithmetic realization at various levels in literature which is surveyed here When we consider floating point unit, addition is at the top level in term of operation intricacy The floating point unit provides with certain amount of delay with significant area Many researchers have worked to reduce the overall latency In order to design an efficient floating point adder the major requisite is improvement in performance, area and latency Multiplication is the most important operation in the field of signal processing Multiplication includes add and shift operation which requires large computation time The main intent behind the design of floating point multiplier unit is to increase the speed so as to improve the performance of the signal processing application A different design paradigm of floating point unit is compared here using Xilinx ISE 131 using device Vertex 5

Lokesh Kamble

Papers

Research trends in development of floating point computer arithmetic