Research trends in development of floating point computer arithmetic

TLDR: The main intent behind the design of floating point multiplier unit is to increase the speed so as to improve the performance of the signal processing application.

Abstract: Most of the today's processor's require fast arithmetic operation with greater accuracy and relies on floating point arithmetic for numerical calculation Addition and multiplication are the keys of floating point arithmetic realization at various levels in literature which is surveyed here When we consider floating point unit, addition is at the top level in term of operation intricacy The floating point unit provides with certain amount of delay with significant area Many researchers have worked to reduce the overall latency In order to design an efficient floating point adder the major requisite is improvement in performance, area and latency Multiplication is the most important operation in the field of signal processing Multiplication includes add and shift operation which requires large computation time The main intent behind the design of floating point multiplier unit is to increase the speed so as to improve the performance of the signal processing application A different design paradigm of floating point unit is compared here using Xilinx ISE 131 using device Vertex 5