A system and methods are provided to design, verify and develop simulated hardware and software components for a desired electrical device The system includes a cycle-accurate simulator where X-number of simulator cycles is equivalent to Y-number of cycles on a simulated hardware component The system further includes a simulator library for modeling and verifying hardware components of a desired electronic device The simulator library includes built-in models and routines for simulating multiple internal hardware components The simulator library is used with the cycle-accurate simulator The system also includes a simulation Application Program Interface ("API") for allowing user-customized model and routines of internal and external hardware components to be used with the cycle-accurate simulator The system can be used to design, verify and develop on-chip and off-chip components for a system-on-a-chip used in a desired electrical device The methods provided include first method to simulate a requested operation for a simulated component far in the future with a fixed-length cycle counter by adjusting internal cycle counts in the cycle-accurate simulator for the requested operation and for the fixed-length cycle counter A second method is used to send a not-ready response for a requested operation, when the requested operation takes longer than an estimated number of cycles in the cycle-accurate simulator The system and methods allow for detecting access errors, bus faults, invalid address translations, privilege protection violations, alignment violations and other timing and behavior violations for simulated hardware and software components and the integration thereof

System and method for simulation of integrated hardware and software components

A method for improving the timing performance of a standard cell ASIC layout. The method is operable at any phase of the ASIC design cycle including following the completion of layout phase placement and routing. The method compares post-layout timing values with pre-layout timing targets for each timing arc associated with each standard cell component of the ASIC design. For each timing arc, a functionally equivalent cell having higher or lower output drive is selected which optimally improves the timing slack on each timing arc. To assure that the method converges and terminates, a list of timing slack values, one for each timing arc of the ASIC design, is constructed in sorted order from worst timing slack to best timing slack. The swap method determines in order from worse timing slack to best a functionally equivalent standard cell which may be swapped to improve the timing slack on the timing arc. Once a standard cell is swapped for a given timing arc, no further swaps need be made for subsequent entries on the sorted list: the timing slack of subsequent entries is assured to be better than the worse timing slack value of an earlier encountered timing arc in the sorted list.

Method for cell swapping to improve pre-layout to post-layout timing

Statistical timing analysis methods for circuits are described which compensate for circuit elements having correlated timing delays with a high degree of computational efficiency. An extended canonical timing model is used to represent each delay element along a circuit path, wherein the model bears information regarding any correlations that each element has to any other elements in the circuit (and/or to any external global factors, e.g., global temperature variations over the circuit, etc.). The model can be represented in a vectorized format which allows enhancement of computational efficiency, wherein the coefficients of the vectors allow an objective measure of element correlation (and wherein the vectors can be “pruned” by dropping insignificant coefficients to further enhance computational efficiency). A decomposition procedure can be used to decompose correlated elements into uncorrelated elements to allow delays to me more easily propagated through the timing diagram representing the circuit. Finally, a bounded approximation for the output of the MAX operator is described which provides a safely conservative approximation regardless of the linearity of the MAX output.

Efficient statistical timing analysis of circuits

Methods, apparatus and computer program products are provided that perform the operations of extracting first estimates of the resistance and capacitance of each of a first plurality of nets in an integrated circuit and then determining, for each of the first plurality of nets, a respective maximum delay model that attributes all of the first estimate of the resistance of the respective net to a front-end of the net and all of the first estimate of the capacitance of the respective net to a back-end of the net. Respective minimum delay models are also obtained for each of the first plurality of nets. Each of these minimum delay models attributes all of the first estimate of the resistance of the respective net to the back-end of the net and all of the first estimate of the capacitance of the respective net to a front-end of the net. These minimum and maximum delay models are then used in the determination of minimum and maximum delay estimates for each of the first plurality of nets. The delay estimates are then used to determine a net timing error bound associated with each net. These net timing error bounds are then filtered against a user-specified net timing error tolerance to determine which nets have an excessive timing error bound. Those nets having excessive timing error bounds are then modeled using more accurate models.

Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits using best and worst case delay models for nets therein

A method, apparatus and computer program product performs a bounded parasitic extraction of typically all nets in an integrated circuit as part of a series of post-layout verification operations. According to one embodiment, a resistance-only extraction and/or a capacitance-only extraction is initially performed using computationally inexpensive electrical models of the nets. The resistance and capacitance extractions may be combined with models of the active devices to generate realistic worst case and best case delay models for each of the extracted nets. The delay models may be based on the resistance-only extraction and an upper bound on the parasitic capacitance of the net determined from the capacitance-only extraction, however, other models based solely on a resistance-only extraction may also be used, although they are typically less preferred. A user-specified timing error tolerance is then used to automatically determine the appropriate level of additional extraction detail to be applied to the specific nets in the integrated circuit. This gives the user direct error control over the extraction process so that the extracted netlist meets the user-specified timing error tolerance in an efficient manner.

Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits by filtering timing error bounds for layout critical nets

A computer automated logic synthesis tool performs a timing analysis during the optimization of a hardware description file including general logic expressions of a prototype circuit by minimizing a delay value for a gate network comprised of logic cells provided in a target library. Minimization occurs by modeling a gate network for a logic expression that orders the input signals into the gate network according to their input delays, and the output delays from assigned logic cells. The output delay for the assigned logic cell is based on intrinsic delays of boolean nodes in the logic cells. The delay for the gate network includes an R-C delay value for gate fan-out, based on the average R-C delay values in the target library. The logic synthesis tool is able to select from among various alternate logically equivalent gate networks, the gate network that provides the minimized timing delay.

Lon-Phon Lin

Papers

Timing analysis for logic optimization using target library delay values