A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

Grooves are formed in a surface of a wafer, on which surface semiconductor elements are formed, along dicing lines. The grooves are deeper than a thickness of a finished chip. A holding member is attached on the surface of the wafer on which the semiconductor elements are formed. A bottom surface of the wafer is lapped and polished to the thickness of the finished chip, thereby dividing the wafer into chips. When the wafer is divided into the chips, the lapping and polishing is continued until the thickness of the wafer becomes equal to the thickness of the finished chip, even after the wafer has been divided into the chips by the lapping and polishing.

Method of dividing a wafer and method of manufacturing a semiconductor device

A method for increasing integrated circuit density is disclosed comprising stacking an upper wafer and a lower wafer, each of which having fabricated circuitry in specific areas on their respective face surfaces. The upper wafer is attached back-to-back with the lower wafer with a layer of adhesive applied over the back side of the lower wafer. The wafers are aligned so as to bring complementary circuitry on each of the wafers into perpendicular alignment. The adhered wafer pair is then itself attached to an adhesive film to immobilize the wafer during dicing. The adhered wafer pair may be diced into individual die pairs or wafer portions containing more than one die pair.

Method of fabrication of stacked semiconductor devices

An Integrated Circuit device, including: a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single crystal transistors, where the second layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of the first transistors that cross the first dice lane, where a plurality of the second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to the plurality of the second transistors that cross the second dice lane, and at least one thermal conducting path from at least one of the second single crystal transistors to an external surface of the device.

3D semiconductor device and structure

A semiconductor device (10) having a termination structure (25) and a reduced on-resistance. The termination structure (25) is fabricated using the same processing steps that were used for manufacturing an active device region (21). The termination structure (25) and the active device region (21) are formed by etching trenches (22, 23) into a drift layer (14). The trenches (22, 23) are filled with a doped polysilicon trench fill material (24), which is subsequently planarized. The semiconductor device (10) is formed in the trenches (22) filled with the polysilicon trench fill material (24) that are in the active region. The trenches (23) filled with the polysilicon trench fill material (24) in a termination region serve as termination structures.

Semiconductor device and method of manufacture

A semiconductor structure is disclosed which reliably provides for very high PN junction reverse breakdown voltages. A very high resistivity film overlying a junction-protecting oxide passivation layer and making electrical contact with the P-type material and the N material of the subject PN junction is utilized to neutralize the effects of accumulated charge on or within the oxide passivation layer. Annular guard rings surrounding and spaced from the subject PN junction may be biased by contacting the high resistivity film, thereby improving the PN junction reverse breakdown voltage. The stability of the shunt leakage current through the high resistivity film is greatly increased by means of a thin, high integrity oxide layer grown or deposited thereon. In integrated circuit structures, parasitic FET paths due to inversion of semiconductor material caused by charge accumulations at the oxide surface are suppressed by judicious electroding, wherein the oxide surface potential over critical regions is set to desired values by judicious extensions of interconnnect metalization and very high resistivity films over the oxide surface, and in intimate contact therewith. The use of the very high resistivity film allows setting of oxide surface potentials over critical areas otherwise unaccessible because of metal interconnect layout limitations.

Implementation of surface sensitive semiconductor devices

A method useful in the backside processing of semiconductor wafers includes providing a semiconductor wafer having a first surface that has been substantially processed. The processed first surface of the semiconductor wafer is bonded to a handle wafer. Once bonded to the handle wafer, backside processing may be performed on the wafer. Following backside processing, the wafer is sawn while still bonded to the handle wafer. The individual dice are then removed from the handle wafer. This process involves fewer handling steps of the semiconductor wafer and the handle wafer provides support to the semiconductor wafer during backside processing thereby reducing opportunities for breakage.

Backside processing method

A vertical conducting insulating gate bipolar transistor having an emitter region formed in a base region wherein the base region is not shorted to the emitter is provided. The emitter and base regions are formed in an upper portion of a lightly doped semiconductor drift region and an anode region is formed in a bottom portion of the drift region. During forward conduction, minority carriers are injected from the anode into the base region, biasing the base region sufficiently to inject minority carriers into the upper surface of the drift region. The injected minority carriers improve conductivity in the upper portion of the drift region.

Conductivity modulated insulated gate semiconductor device

Magnetically sensitive semiconductor elements suitable for fabrication in monolithic integrated circuits are disclosed. The elements comprise a semiconductor region of one conductivity type with contact means for providing current flow generally parallel to a major axis, a second orthogonal axis for the application of a magnetic field, and yet a third mutually orthogonal axis along which are disposed at least three second type conductivity regions forming in combination with the first major region a transistor structure with differential properties. In some of the embodiments, low magnetic offset is provided by a selfaligning feature, and power comsumption is minimized by a high resistance region in the device.

Semiconductor magnetic transducers

A semiconductor device having a conductive recombination layer. The conductive recombination layer, comprised of doped polycrystalline material, doped polycrystalline material and tungsten silicide, or tungsten silicide, is disposed between two separate semiconductor substrates which are bonded together using a polished surface on the conductive recombination layer as one of the bonding interfaces. The conductive recombination layer recombines minority carriers and thereby increases the switching speed of the device.

Lowell E. Clark

Papers

Implementation of surface sensitive semiconductor devices

Backside processing method

Conductivity modulated insulated gate semiconductor device

Semiconductor magnetic transducers

Bipolar semiconductor device having a conductive recombination layer