A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

Logic circuit, processing unit, electronic component, and electronic device

An integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells. Each flip-flop cell includes a master latch that receives a first data signal and generates a first latch signal, a slave latch that receives the first latch signal and generates a second latch signal, and a multiplexer having first and second inputs respectively connected to the master and slave latches for receiving a first input signal and the second latch signal, and generating a scan data output signal depending on a trig signal. The first input signal is one of the first data signal and the first latch signal. The clock signal provided to the slave latch is gated by the trig signal.

Integrated circuit with low power scan system

An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.

Vectored flip-flop

A register circuit includes a first pulse-latch circuit configured to store data from a first input node. A multiplexer circuit is configured to select between an output of the first pulse-latch circuit and a second input node. A second pulse-latch circuit is configured to store data provided by the multiplexer circuit. A control circuit is configured to switch, in response to a configuration signal, the register circuit between a flip-flop mode and a dual-latch mode.

Multimode registers with pulse latches

A flip-flop circuit is provided. The flip-flop circuit receives a test signal at a test-in terminal and a data signal at a data-in terminal and generates a scan-out signal. The flip-flop circuit includes a buffer and a scan flip-flop. The buffer has an input terminal coupled to the test-in terminal and an output terminal and further has a first power terminal and a second power terminal. The buffer operates to generate a buffering signal. The scan flip-flop receives the buffering signal and the data signal. The scan flip-flop is controlled by a test-enable signal to generate the scan-out signal according to the buffering signal or the data signal. The scan flip-flop further generates a test-enable reverse signal which is the reverse of the test-enable signal. The first power terminal of the buffer receives the test-enable signal or the test-enable reverse signal.

Flip-flop circuit and scan chain using the same

A scan-testable integrated circuit includes first and second flip-flops. The first flip-flop includes first and second latches and the second flip-flop includes third and fourth latches and a logic circuit. During scan-shift mode of scan testing, the first flip-flop shifts a first bit of a test pattern into the second flip-flop. The first flip-flop then shifts a second bit of the test pattern into the second flip-flop. The logic circuit deactivates a clock signal provided to the third latch, which is a master latch, when the logic states of the first and second bits are equal. The output terminals of the third and fourth latches are retained at the logic state corresponding to the first bit, thereby reducing power consumption.

Integrated circuit with low power scan flip-flop

The invention relates to an integrated circuit with low-power scanning triggers. The scanning-testing integrated circuit comprises a first trigger and a second trigger. The first trigger comprises a first latch register and a second latch register, and the second trigger comprises a third latch register, a fourth latch register and a logic circuit. In a scanning-shifting mode period of a scanning test, the first trigger moves a first bit of a testing template into the second trigger, and then the first trigger moves a second bit of the testing template into the second trigger. When the logic states of the first bit and the second bit are the same, the logic circuit invalidates a clock signal provided to the third latch register, wherein the third latch register is the main latch register. Output terminals of the third latch register and the fourth latch register are kept at the logic state corresponding to the first bit, so that the power loss is reduced.

Lu Sian

Papers

Integrated circuit with low power scan flip-flop

Integrated circuit with low-power scanning triggers