Patent
Integrated circuit with low power scan flip-flop
TLDR
In this article, a scan-testable integrated circuit includes first and second flip-flops and a logic circuit, and the logic circuit deactivates a clock signal provided to the third latch, which is a master latch.Abstract:
A scan-testable integrated circuit includes first and second flip-flops. The first flip-flop includes first and second latches and the second flip-flop includes third and fourth latches and a logic circuit. During scan-shift mode of scan testing, the first flip-flop shifts a first bit of a test pattern into the second flip-flop. The first flip-flop then shifts a second bit of the test pattern into the second flip-flop. The logic circuit deactivates a clock signal provided to the third latch, which is a master latch, when the logic states of the first and second bits are equal. The output terminals of the third and fourth latches are retained at the logic state corresponding to the first bit, thereby reducing power consumption.read more
Citations
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Patent
Logic circuit, processing unit, electronic component, and electronic device
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TL;DR: In this article, a register circuit includes a first pulse-latch circuit configured to store data from a first input node, and a control circuit is configured to switch, in response to a configuration signal, the register circuit between a flip-flop mode and a duallatch mode.
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TL;DR: An SEU immune flip-flop as discussed by the authors includes a master stage data latch having an input, an output, a clock input, being transparent in response to a clock signal first state and being latched on response to clock signal second state.
References
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Patent
Low power flip-flop circuit and method thereof
TL;DR: In this article, a low power flip-flop circuit with a clocked flip flop (10) and a switching circuit (40, 60) with control inputs coupled to the data input and data output of the flipflop is described.
Patent
Dynamically reconfigurable shared scan-in test architecture
Rohit Kapur,Nodari Sitchinava,Samitha Samaranayake,Emil Gizdarski,Frederic J. Neuveux,Suryanarayana Duggirala,T.W. Williams +6 more
TL;DR: In this article, a low overhead dynamically reconfigurable shared scan-in test architecture is provided, which allows for changing scan inputs during the scan operation on a per-shift basis.
Patent
Scan chain element and associated method
TL;DR: In this article, a scan chain element in an integrated circuit, including a first latch to accept test data as an input, a second latch connected to accept the output of the first latch as an output, control logic for accepting a clock signal and a hold signal, is presented.
Patent
Low power flip flop through partially gated slave clock
TL;DR: In this paper, a system and method for reducing power consumption within a flip-flop circuit on a semiconductor chip is presented, where a gated input clock signal is received by a slave latch.
Patent
Method and system for clock skew independent scan register chains
TL;DR: In this paper, a method for clock skew independent scan chains is presented. But it does not specify a scan mode for the mux-D scan register and does not provide a scan-enable signal.