An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.

Method and apparatus for shared I/O in a load/store fabric

An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of operating system domains through a PCI Express fabric. Each of the first plurality of I/O ports is configured to route PCI Express transactions between said plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint, where the first shared input/output endpoint is configured to request/complete said PCI Express transactions for each of the plurality of operating system domains. The core logic is coupled to the first plurality of I/O ports and the second I/O port. The core logic routes the PCI Express transactions between the first plurality of I/O ports and the second I/O port.

Switching apparatus and method for providing shared i/o within a load-store fabric

A shared network interface controller (NIC) interfaces a plurality of operating system domains as part of the load-store architecture of the operating system domains. A bus interface couples the NIC to a load-store domain bus (such as PCI-Express), using header information to associate data on the bus with an originating operating system domain. Transmit/receive logic connects the NIC to the network. Association logic allows the NIC to designate, and later lookup which destination MAC address (on the Ethernet side) is associated with which operating system domain. Descriptor register files and Control Status Registers (CSR's) specific to an operating system domain are duplicated and made available for each domain. Several direct memory access (DMA) engines are provided to improve throughput. Packet replication logic, filters (perfect and hash) and VLAN tables are used for looping back packets originating from one operating system domain to another and other operations.

Method and apparatus for a shared I/O network interface controller

A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The memory devices are mounted in mirrored configuration with mirrored terminals of memory devices on opposite surfaces being interconnected. A memory hub mounted on each module alters the configuration of address and/or command signals coupled to the memory devices depending upon whether the memory devices on the first surface of the substrate or the memory devices on the second surface of the substrate are being accessed. Alternatively, the configuration of the address and/or command signals coupled to mirrored memory devices may be altered by a register mounted on the substrate that is coupled to the memory devices or by a memory controller coupled directly to memory devices on one or more memory modules.

Dynamic command and/or address mirroring system and method for memory modules

Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability.

Dynamically modulating link width

A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation

Apparatus, system, and method for bus link width optimization

A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation.

Apparatus, system, and method for bus link width optimization of a graphics system

A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, clock buffers not required to drive active data lanes are placed in an inactive state to reduce clock power dissipation.

Logical-to-physical lane assignment to reduce clock power dissipation in a bus having a variable link width

A method and system for supporting multiple display interface standards are disclosed. Specifically, one embodiment of the present invention sets forth a computing device, which includes a processing unit and a display interface. The display interface further includes a formatting logic and a set of output pins, wherein the formatting logic is configured to derive a first set of output signals conforming to a first display interface standard from a data stream, drive the first set of output signals via a set of output pins to a first display device supporting the first display interface standard, support a second display interface standard instead of the first display interface standard in response to a state change and derive the first set of output signals conforming to the second display interface standard, and drive the first set of output signals via the same set of output pins to a second display device supporting the second display interface standard.

Method and system for supporting multiple display interface standards

One embodiment of a field changeable rendering system includes an output device interfaced to a motherboard, a fixed rendering device mounted to the motherboard for generating information to be output on said output device, a connector for attaching a field-changeable rendering card to the motherboard, said field-changeable rendering card capable of housing a discrete rendering device for generating information to be output on said output device and detection circuitry for detecting that a field-changeable rendering card housing a discrete rendering device is coupled to said connector and causing information from said field-changeable rendering card housing a discrete rendering device to be output on said output device. One advantage of the disclosed edge connector is that it is compatible with a plurality of graphics cards and systems, thereby enabling a computing device user to upgrade the existing device's graphics system. Thus, the user is not forced to purchase an entirely new computing device in order to take advantage of graphics innovations. A further advantage of the disclosed edge connector is that it enables upgrades to low voltage differential signaling (LVDS) features, without the need for additional costly devices capable of operating at LVDS data rates.

Luc R. Bisson

Papers

Apparatus, system, and method for bus link width optimization

Apparatus, system, and method for bus link width optimization of a graphics system

Logical-to-physical lane assignment to reduce clock power dissipation in a bus having a variable link width

Method and system for supporting multiple display interface standards

Field Changeable Rendering System For A Computing Device